clk: meson: mpll: fix mpll0 fractional part ignored
mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c ("clk: meson: mpll: add rw operation") Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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