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提交 1e09939b 编写于 作者: A Arnd Bergmann
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Merge branch 'next-samsung-devel' of... 

Merge branch 'next-samsung-devel' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/devel
上级 4d09a938 e8de616e
展开全部 隐藏空白更改
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Showing with 2717 addition and 1314 deletion
arch/arm/Kconfig
浏览文件 @ 1e09939b
...@@ -684,6 +684,7 @@ config ARCH_S3C2410 ...@@ -684,6 +684,7 @@ config ARCH_S3C2410
select GENERIC_GPIO select GENERIC_GPIO
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select ARCH_USES_GETTIMEOFFSET select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
help help
...@@ -701,6 +702,7 @@ config ARCH_S3C64XX ...@@ -701,6 +702,7 @@ config ARCH_S3C64XX
select CPU_V6 select CPU_V6
select ARM_VIC select ARM_VIC
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select NO_IOPORT select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET select ARCH_USES_GETTIMEOFFSET
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
...@@ -725,6 +727,7 @@ config ARCH_S5P64X0 ...@@ -725,6 +727,7 @@ config ARCH_S5P64X0
select CPU_V6 select CPU_V6
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C2410_WATCHDOG if WATCHDOG
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK select HAVE_SCHED_CLOCK
...@@ -738,6 +741,7 @@ config ARCH_S5PC100 ...@@ -738,6 +741,7 @@ config ARCH_S5PC100
bool "Samsung S5PC100" bool "Samsung S5PC100"
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select CPU_V7 select CPU_V7
select ARM_L1_CACHE_SHIFT_6 select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET select ARCH_USES_GETTIMEOFFSET
...@@ -751,8 +755,10 @@ config ARCH_S5PV210 ...@@ -751,8 +755,10 @@ config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110" bool "Samsung S5PV210/S5PC110"
select CPU_V7 select CPU_V7
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select ARM_L1_CACHE_SHIFT_6 select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
...@@ -767,8 +773,10 @@ config ARCH_EXYNOS4 ...@@ -767,8 +773,10 @@ config ARCH_EXYNOS4
bool "Samsung EXYNOS4" bool "Samsung EXYNOS4"
select CPU_V7 select CPU_V7
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C_RTC if RTC_CLASS
......
arch/arm/common/gic.c
浏览文件 @ 1e09939b
...@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock); ...@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
/* Address of GIC 0 CPU interface */ /* Address of GIC 0 CPU interface */
void __iomem *gic_cpu_base_addr __read_mostly; void __iomem *gic_cpu_base_addr __read_mostly;
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __iomem *cpu_base;
};
/* /*
* Supported arch specific GIC irq extension. * Supported arch specific GIC irq extension.
* Default make them NULL. * Default make them NULL.
......
arch/arm/include/asm/hardware/gic.h
浏览文件 @ 1e09939b
...@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int); ...@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
void gic_enable_ppi(unsigned int); void gic_enable_ppi(unsigned int);
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __iomem *cpu_base;
};
#endif #endif
#endif #endif
arch/arm/mach-exynos4/Kconfig
浏览文件 @ 1e09939b
...@@ -16,7 +16,8 @@ config CPU_EXYNOS4210 ...@@ -16,7 +16,8 @@ config CPU_EXYNOS4210
Enable EXYNOS4210 CPU support Enable EXYNOS4210 CPU support
config EXYNOS4_MCT config EXYNOS4_MCT
bool "Kernel timer support by MCT" bool
default y
help help
Use MCT (Multi Core Timer) as kernel timers Use MCT (Multi Core Timer) as kernel timers
...@@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI ...@@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI
help help
Compile in platform device definitions for AHCI Compile in platform device definitions for AHCI
config EXYNOS4_SETUP_FIMD0
bool
help
Common setup code for FIMD0.
config EXYNOS4_DEV_PD config EXYNOS4_DEV_PD
bool bool
help help
...@@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU ...@@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU
help help
Common setup code for SYSTEM MMU in EXYNOS4 Common setup code for SYSTEM MMU in EXYNOS4
config EXYNOS4_DEV_DWMCI
bool
help
Compile in platform device definitions for DWMCI
config EXYNOS4_SETUP_I2C1 config EXYNOS4_SETUP_I2C1
bool bool
help help
...@@ -103,6 +114,7 @@ menu "EXYNOS4 Machines" ...@@ -103,6 +114,7 @@ menu "EXYNOS4 Machines"
config MACH_SMDKC210 config MACH_SMDKC210
bool "SMDKC210" bool "SMDKC210"
select CPU_EXYNOS4210 select CPU_EXYNOS4210
select S5P_DEV_FIMD0
select S3C_DEV_RTC select S3C_DEV_RTC
select S3C_DEV_WDT select S3C_DEV_WDT
select S3C_DEV_I2C1 select S3C_DEV_I2C1
...@@ -112,6 +124,7 @@ config MACH_SMDKC210 ...@@ -112,6 +124,7 @@ config MACH_SMDKC210
select S3C_DEV_HSMMC3 select S3C_DEV_HSMMC3
select EXYNOS4_DEV_PD select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_SDHCI select EXYNOS4_SETUP_SDHCI
help help
...@@ -120,6 +133,7 @@ config MACH_SMDKC210 ...@@ -120,6 +133,7 @@ config MACH_SMDKC210
config MACH_SMDKV310 config MACH_SMDKV310
bool "SMDKV310" bool "SMDKV310"
select CPU_EXYNOS4210 select CPU_EXYNOS4210
select S5P_DEV_FIMD0
select S3C_DEV_RTC select S3C_DEV_RTC
select S3C_DEV_WDT select S3C_DEV_WDT
select S3C_DEV_I2C1 select S3C_DEV_I2C1
...@@ -127,9 +141,11 @@ config MACH_SMDKV310 ...@@ -127,9 +141,11 @@ config MACH_SMDKV310
select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3 select S3C_DEV_HSMMC3
select EXYNOS4_DEV_AHCI
select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_KEYPAD
select EXYNOS4_DEV_PD select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI select EXYNOS4_SETUP_SDHCI
...@@ -153,13 +169,22 @@ config MACH_ARMLEX4210 ...@@ -153,13 +169,22 @@ config MACH_ARMLEX4210
config MACH_UNIVERSAL_C210 config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board" bool "Mobile UNIVERSAL_C210 Board"
select CPU_EXYNOS4210 select CPU_EXYNOS4210
select S5P_GPIO_INT
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
select S3C_DEV_HSMMC select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3 select S3C_DEV_HSMMC3
select S3C_DEV_I2C1 select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5 select S3C_DEV_I2C5
select S5P_DEV_MFC
select S5P_DEV_ONENAND select S5P_DEV_ONENAND
select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5 select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI select EXYNOS4_SETUP_SDHCI
help help
...@@ -176,13 +201,16 @@ config MACH_NURI ...@@ -176,13 +201,16 @@ config MACH_NURI
select S3C_DEV_I2C1 select S3C_DEV_I2C1
select S3C_DEV_I2C3 select S3C_DEV_I2C3
select S3C_DEV_I2C5 select S3C_DEV_I2C5
select S5P_DEV_MFC
select S5P_DEV_USB_EHCI select S5P_DEV_USB_EHCI
select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3 select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5 select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY select EXYNOS4_SETUP_USB_PHY
select SAMSUNG_DEV_PWM select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_ADC
help help
Machine support for Samsung Mobile NURI Board. Machine support for Samsung Mobile NURI Board.
......
arch/arm/mach-exynos4/Makefile
浏览文件 @ 1e09939b
...@@ -13,19 +13,14 @@ obj- := ...@@ -13,19 +13,14 @@ obj- :=
# Core support for EXYNOS4 system # Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o
ifeq ($(CONFIG_EXYNOS4_MCT),y) obj-$(CONFIG_EXYNOS4_MCT) += mct.o
obj-y += mct.o
else
obj-y += time.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
endif
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
...@@ -43,8 +38,10 @@ obj-y += dev-audio.o ...@@ -43,8 +38,10 @@ obj-y += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
......
arch/arm/mach-exynos4/clock.c
浏览文件 @ 1e09939b
此差异已折叠。
arch/arm/mach-exynos4/cpu.c
浏览文件 @ 1e09939b
...@@ -16,12 +16,16 @@ ...@@ -16,12 +16,16 @@
#include <asm/proc-fns.h> #include <asm/proc-fns.h>
#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/clock.h> #include <plat/clock.h>
#include <plat/devs.h>
#include <plat/exynos4.h> #include <plat/exynos4.h>
#include <plat/adc-core.h>
#include <plat/sdhci.h> #include <plat/sdhci.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/fb-core.h>
#include <plat/fimc-core.h> #include <plat/fimc-core.h>
#include <plat/iic-core.h> #include <plat/iic-core.h>
...@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = { ...@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
} }, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
.length = SZ_64K,
.type = MT_DEVICE,
},
}; };
static void exynos4_idle(void) static void exynos4_idle(void)
...@@ -129,6 +143,8 @@ void __init exynos4_map_io(void) ...@@ -129,6 +143,8 @@ void __init exynos4_map_io(void)
exynos4_default_sdhci2(); exynos4_default_sdhci2();
exynos4_default_sdhci3(); exynos4_default_sdhci3();
s3c_adc_setname("samsung-adc-v3");
s3c_fimc_setname(0, "exynos4-fimc"); s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc"); s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc"); s3c_fimc_setname(2, "exynos4-fimc");
...@@ -138,6 +154,8 @@ void __init exynos4_map_io(void) ...@@ -138,6 +154,8 @@ void __init exynos4_map_io(void)
s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c"); s3c_i2c2_setname("s3c2440-i2c");
s5p_fb_setname(0, "exynos4-fb");
} }
void __init exynos4_init_clocks(int xtal) void __init exynos4_init_clocks(int xtal)
...@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal) ...@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks(); exynos4_setup_clocks();
} }
static void exynos4_gic_irq_eoi(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
gic_data->cpu_base = S5P_VA_GIC_CPU +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
}
void __init exynos4_init_irq(void) void __init exynos4_init_irq(void)
{ {
int irq; int irq;
gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
for (irq = 0; irq < MAX_COMBINER_NR; irq++) { for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
/*
* From SPI(0) to SPI(39) and SPI(51), SPI(53) are
* connected to the interrupt combiner. These irqs
* should be initialized to support cascade interrupt.
*/
if ((irq >= 40) && !(irq == 51) && !(irq == 53))
continue;
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0)); COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq)); combiner_cascade_irq(irq, IRQ_SPI(irq));
......
arch/arm/mach-exynos4/dev-audio.c
浏览文件 @ 1e09939b
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <mach/map.h> #include <mach/map.h>
#include <mach/dma.h> #include <mach/dma.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/regs-audss.h>
static const char *rclksrc[] = { static const char *rclksrc[] = {
[0] = "busclk", [0] = "busclk",
...@@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = { ...@@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR, | QUIRK_NEED_RSTCLR,
.src_clk = rclksrc, .src_clk = rclksrc,
.idma_addr = EXYNOS4_AUDSS_INT_MEM,
}, },
}, },
}; };
......
arch/arm/mach-exynos4/dev-dwmci.c 0 → 100644
浏览文件 @ 1e09939b
/*
* linux/arch/arm/mach-exynos4/dev-dwmci.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Platform device for Synopsys DesignWare Mobile Storage IP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mmc/dw_mmc.h>
#include <plat/devs.h>
#include <mach/map.h>
static int exynos4_dwmci_get_bus_wd(u32 slot_id)
{
return 4;
}
static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
{
return 0;
}
static struct resource exynos4_dwmci_resource[] = {
[0] = {
.start = EXYNOS4_PA_DWMCI,
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DWMCI,
.end = IRQ_DWMCI,
.flags = IORESOURCE_IRQ,
}
};
static struct dw_mci_board exynos4_dwci_pdata = {
.num_slots = 1,
.quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
.bus_hz = 80 * 1000 * 1000,
.detect_delay_ms = 200,
.init = exynos4_dwmci_init,
.get_bus_wd = exynos4_dwmci_get_bus_wd,
};
static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
struct platform_device exynos4_device_dwmci = {
.name = "dw_mmc",
.id = -1,
.num_resources = ARRAY_SIZE(exynos4_dwmci_resource),
.resource = exynos4_dwmci_resource,
.dev = {
.dma_mask = &exynos4_dwmci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &exynos4_dwci_pdata,
},
};
void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
{
struct dw_mci_board *npd;
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
&exynos4_device_dwmci);
if (!npd->init)
npd->init = exynos4_dwmci_init;
if (!npd->get_bus_wd)
npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
}
arch/arm/mach-exynos4/hotplug.c
浏览文件 @ 1e09939b
...@@ -13,9 +13,12 @@ ...@@ -13,9 +13,12 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/smp.h> #include <linux/smp.h>
#include <linux/io.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <mach/regs-pmu.h>
extern volatile int pen_release; extern volatile int pen_release;
static inline void cpu_enter_lowpower(void) static inline void cpu_enter_lowpower(void)
...@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void) ...@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
static inline void platform_do_lowpower(unsigned int cpu, int *spurious) static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{ {
/*
* there is no power-control hardware on this platform, so all
* we can do is put the core into WFI; this is safe as the calling
* code will have already disabled interrupts
*/
for (;;) { for (;;) {
/* make cpu1 to be turned off at next WFI command */
if (cpu == 1)
__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
/* /*
* here's the WFI * here's the WFI
*/ */
......
arch/arm/mach-exynos4/include/mach/clkdev.h 0 → 100644
浏览文件 @ 1e09939b
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif
arch/arm/mach-exynos4/localtimer.c → arch/arm/mach-exynos4/include/mach/dwmci.h
浏览文件 @ 1e09939b
/* linux/arch/arm/mach-exynos4/localtimer.c /* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
* *
* Cloned from linux/arch/arm/mach-realview/localtimer.c * Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* *
* Copyright (C) 2002 ARM Ltd. * Synopsys DesignWare Mobile Storage for EXYNOS4210
* All Rights Reserved
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <linux/clockchips.h> #ifndef __ASM_ARM_ARCH_DWMCI_H
#define __ASM_ARM_ARCH_DWMCI_H __FILE__
#include <asm/irq.h> #include <linux/mmc/dw_mmc.h>
#include <asm/localtimer.h>
/* extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
* Setup the local clock events for a CPU.
*/ #endif /* __ASM_ARM_ARCH_DWMCI_H */
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
evt->irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
}
arch/arm/mach-exynos4/include/mach/entry-macro.S
浏览文件 @ 1e09939b
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
*/ */
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/map.h>
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
.macro disable_fiq .macro disable_fiq
...@@ -18,6 +19,10 @@ ...@@ -18,6 +19,10 @@
.macro get_irqnr_preamble, base, tmp .macro get_irqnr_preamble, base, tmp
ldr \base, =gic_cpu_base_addr ldr \base, =gic_cpu_base_addr
ldr \base, [\base] ldr \base, [\base]
mrc p15, 0, \tmp, c0, c0, 5
and \tmp, \tmp, #3
cmp \tmp, #1
addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
.endm .endm
.macro arch_ret_to_user, tmp1, tmp2 .macro arch_ret_to_user, tmp1, tmp2
...@@ -75,10 +80,4 @@ ...@@ -75,10 +80,4 @@
/* As above, this assumes that irqstat and base are preserved.. */ /* As above, this assumes that irqstat and base are preserved.. */
.macro test_for_ltirq, irqnr, irqstat, base, tmp .macro test_for_ltirq, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
mov \tmp, #0
cmp \irqnr, #29
moveq \tmp, #1
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm .endm
arch/arm/mach-exynos4/include/mach/irqs.h
浏览文件 @ 1e09939b
...@@ -19,40 +19,105 @@ ...@@ -19,40 +19,105 @@
#define IRQ_PPI(x) S5P_IRQ(x+16) #define IRQ_PPI(x) S5P_IRQ(x+16)
#define IRQ_LOCALTIMER IRQ_PPI(13)
/* SPI: Shared Peripheral Interrupt */ /* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32) #define IRQ_SPI(x) S5P_IRQ(x+32)
#define IRQ_MCT1 IRQ_SPI(35) #define IRQ_EINT0 IRQ_SPI(16)
#define IRQ_EINT1 IRQ_SPI(17)
#define IRQ_EINT0 IRQ_SPI(40) #define IRQ_EINT2 IRQ_SPI(18)
#define IRQ_EINT1 IRQ_SPI(41) #define IRQ_EINT3 IRQ_SPI(19)
#define IRQ_EINT2 IRQ_SPI(42) #define IRQ_EINT4 IRQ_SPI(20)
#define IRQ_EINT3 IRQ_SPI(43) #define IRQ_EINT5 IRQ_SPI(21)
#define IRQ_USB_HSOTG IRQ_SPI(44) #define IRQ_EINT6 IRQ_SPI(22)
#define IRQ_USB_HOST IRQ_SPI(45) #define IRQ_EINT7 IRQ_SPI(23)
#define IRQ_MODEM_IF IRQ_SPI(46) #define IRQ_EINT8 IRQ_SPI(24)
#define IRQ_ROTATOR IRQ_SPI(47) #define IRQ_EINT9 IRQ_SPI(25)
#define IRQ_JPEG IRQ_SPI(48) #define IRQ_EINT10 IRQ_SPI(26)
#define IRQ_2D IRQ_SPI(49) #define IRQ_EINT11 IRQ_SPI(27)
#define IRQ_PCIE IRQ_SPI(50) #define IRQ_EINT12 IRQ_SPI(28)
#define IRQ_MCT0 IRQ_SPI(51) #define IRQ_EINT13 IRQ_SPI(29)
#define IRQ_MFC IRQ_SPI(52) #define IRQ_EINT14 IRQ_SPI(30)
#define IRQ_AUDIO_SS IRQ_SPI(54) #define IRQ_EINT15 IRQ_SPI(31)
#define IRQ_AC97 IRQ_SPI(55) #define IRQ_EINT16_31 IRQ_SPI(32)
#define IRQ_SPDIF IRQ_SPI(56)
#define IRQ_KEYPAD IRQ_SPI(57) #define IRQ_PDMA0 IRQ_SPI(35)
#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58) #define IRQ_PDMA1 IRQ_SPI(36)
#define IRQ_SLIMBUS IRQ_SPI(59) #define IRQ_TIMER0_VIC IRQ_SPI(37)
#define IRQ_PMU IRQ_SPI(60) #define IRQ_TIMER1_VIC IRQ_SPI(38)
#define IRQ_TSI IRQ_SPI(61) #define IRQ_TIMER2_VIC IRQ_SPI(39)
#define IRQ_SATA IRQ_SPI(62) #define IRQ_TIMER3_VIC IRQ_SPI(40)
#define IRQ_GPS IRQ_SPI(63) #define IRQ_TIMER4_VIC IRQ_SPI(41)
#define IRQ_MCT_L0 IRQ_SPI(42)
#define IRQ_WDT IRQ_SPI(43)
#define IRQ_RTC_ALARM IRQ_SPI(44)
#define IRQ_RTC_TIC IRQ_SPI(45)
#define IRQ_GPIO_XB IRQ_SPI(46)
#define IRQ_GPIO_XA IRQ_SPI(47)
#define IRQ_MCT_L1 IRQ_SPI(48)
#define IRQ_UART0 IRQ_SPI(52)
#define IRQ_UART1 IRQ_SPI(53)
#define IRQ_UART2 IRQ_SPI(54)
#define IRQ_UART3 IRQ_SPI(55)
#define IRQ_UART4 IRQ_SPI(56)
#define IRQ_MCT_G0 IRQ_SPI(57)
#define IRQ_IIC IRQ_SPI(58)
#define IRQ_IIC1 IRQ_SPI(59)
#define IRQ_IIC2 IRQ_SPI(60)
#define IRQ_IIC3 IRQ_SPI(61)
#define IRQ_IIC4 IRQ_SPI(62)
#define IRQ_IIC5 IRQ_SPI(63)
#define IRQ_IIC6 IRQ_SPI(64)
#define IRQ_IIC7 IRQ_SPI(65)
#define IRQ_USB_HOST IRQ_SPI(70)
#define IRQ_USB_HSOTG IRQ_SPI(71)
#define IRQ_MODEM_IF IRQ_SPI(72)
#define IRQ_HSMMC0 IRQ_SPI(73)
#define IRQ_HSMMC1 IRQ_SPI(74)
#define IRQ_HSMMC2 IRQ_SPI(75)
#define IRQ_HSMMC3 IRQ_SPI(76)
#define IRQ_DWMCI IRQ_SPI(77)
#define IRQ_MIPICSI0 IRQ_SPI(78)
#define IRQ_MIPICSI1 IRQ_SPI(80)
#define IRQ_ONENAND_AUDI IRQ_SPI(82)
#define IRQ_ROTATOR IRQ_SPI(83)
#define IRQ_FIMC0 IRQ_SPI(84)
#define IRQ_FIMC1 IRQ_SPI(85)
#define IRQ_FIMC2 IRQ_SPI(86)
#define IRQ_FIMC3 IRQ_SPI(87)
#define IRQ_JPEG IRQ_SPI(88)
#define IRQ_2D IRQ_SPI(89)
#define IRQ_PCIE IRQ_SPI(90)
#define IRQ_MFC IRQ_SPI(94)
#define IRQ_AUDIO_SS IRQ_SPI(96)
#define IRQ_I2S0 IRQ_SPI(97)
#define IRQ_I2S1 IRQ_SPI(98)
#define IRQ_I2S2 IRQ_SPI(99)
#define IRQ_AC97 IRQ_SPI(100)
#define IRQ_SPDIF IRQ_SPI(104)
#define IRQ_ADC0 IRQ_SPI(105)
#define IRQ_PEN0 IRQ_SPI(106)
#define IRQ_ADC1 IRQ_SPI(107)
#define IRQ_PEN1 IRQ_SPI(108)
#define IRQ_KEYPAD IRQ_SPI(109)
#define IRQ_PMU IRQ_SPI(110)
#define IRQ_GPS IRQ_SPI(111)
#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
#define IRQ_SLIMBUS IRQ_SPI(113)
#define IRQ_TSI IRQ_SPI(115)
#define IRQ_SATA IRQ_SPI(116)
#define MAX_IRQ_IN_COMBINER 8 #define MAX_IRQ_IN_COMBINER 8
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) #define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) #define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) #define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
...@@ -73,75 +138,14 @@ ...@@ -73,75 +138,14 @@
#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) #define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) #define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
#define IRQ_PDMA0 COMBINER_IRQ(21, 0) #define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
#define IRQ_PDMA1 COMBINER_IRQ(21, 1) #define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
#define IRQ_UART0 COMBINER_IRQ(26, 0)
#define IRQ_UART1 COMBINER_IRQ(26, 1)
#define IRQ_UART2 COMBINER_IRQ(26, 2)
#define IRQ_UART3 COMBINER_IRQ(26, 3)
#define IRQ_UART4 COMBINER_IRQ(26, 4)
#define IRQ_IIC COMBINER_IRQ(27, 0)
#define IRQ_IIC1 COMBINER_IRQ(27, 1)
#define IRQ_IIC2 COMBINER_IRQ(27, 2)
#define IRQ_IIC3 COMBINER_IRQ(27, 3)
#define IRQ_IIC4 COMBINER_IRQ(27, 4)
#define IRQ_IIC5 COMBINER_IRQ(27, 5)
#define IRQ_IIC6 COMBINER_IRQ(27, 6)
#define IRQ_IIC7 COMBINER_IRQ(27, 7)
#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
#define IRQ_EINT4 COMBINER_IRQ(37, 0)
#define IRQ_EINT5 COMBINER_IRQ(37, 1)
#define IRQ_EINT6 COMBINER_IRQ(37, 2)
#define IRQ_EINT7 COMBINER_IRQ(37, 3)
#define IRQ_EINT8 COMBINER_IRQ(38, 0)
#define IRQ_EINT9 COMBINER_IRQ(38, 1)
#define IRQ_EINT10 COMBINER_IRQ(38, 2)
#define IRQ_EINT11 COMBINER_IRQ(38, 3)
#define IRQ_EINT12 COMBINER_IRQ(38, 4)
#define IRQ_EINT13 COMBINER_IRQ(38, 5)
#define IRQ_EINT14 COMBINER_IRQ(38, 6)
#define IRQ_EINT15 COMBINER_IRQ(38, 7)
#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
#define IRQ_WDT COMBINER_IRQ(53, 0) #define MAX_COMBINER_NR 16
#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
#define MAX_COMBINER_NR 54 #define IRQ_ADC IRQ_ADC0
#define IRQ_TC IRQ_PEN0
#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) #define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
...@@ -155,6 +159,6 @@ ...@@ -155,6 +159,6 @@
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
/* Set the default NR_IRQS */ /* Set the default NR_IRQS */
#define NR_IRQS (IRQ_GPIO_END) #define NR_IRQS (IRQ_GPIO_END + 64)
#endif /* __ASM_ARCH_IRQS_H */ #endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-exynos4/include/mach/map.h
浏览文件 @ 1e09939b
...@@ -57,12 +57,14 @@ ...@@ -57,12 +57,14 @@
#define EXYNOS4_PA_DMC0 0x10400000 #define EXYNOS4_PA_DMC0 0x10400000
#define EXYNOS4_PA_COMBINER 0x10448000 #define EXYNOS4_PA_COMBINER 0x10440000
#define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000
#define EXYNOS4_GIC_BANK_OFFSET 0x8000
#define EXYNOS4_PA_COREPERI 0x10500000 #define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_GIC_CPU 0x10500100
#define EXYNOS4_PA_TWD 0x10500600 #define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_GIC_DIST 0x10501000
#define EXYNOS4_PA_L2CC 0x10502000 #define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_MDMA 0x10810000 #define EXYNOS4_PA_MDMA 0x10810000
...@@ -93,7 +95,10 @@ ...@@ -93,7 +95,10 @@
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 #define EXYNOS4_PA_MIPI_CSIS0 0x11880000
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 #define EXYNOS4_PA_MIPI_CSIS1 0x11890000
#define EXYNOS4_PA_FIMD0 0x11C00000
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define EXYNOS4_PA_DWMCI 0x12550000
#define EXYNOS4_PA_SATA 0x12560000 #define EXYNOS4_PA_SATA 0x12560000
#define EXYNOS4_PA_SATAPHY 0x125D0000 #define EXYNOS4_PA_SATAPHY 0x125D0000
...@@ -103,11 +108,15 @@ ...@@ -103,11 +108,15 @@
#define EXYNOS4_PA_EHCI 0x12580000 #define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_HSPHY 0x125B0000 #define EXYNOS4_PA_HSPHY 0x125B0000
#define EXYNOS4_PA_MFC 0x13400000
#define EXYNOS4_PA_UART 0x13800000 #define EXYNOS4_PA_UART 0x13800000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS4_PA_ADC 0x13910000
#define EXYNOS4_PA_ADC1 0x13911000
#define EXYNOS4_PA_AC97 0x139A0000 #define EXYNOS4_PA_AC97 0x139A0000
#define EXYNOS4_PA_SPDIF 0x139B0000 #define EXYNOS4_PA_SPDIF 0x139B0000
...@@ -130,6 +139,8 @@ ...@@ -130,6 +139,8 @@
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
#define S3C_PA_RTC EXYNOS4_PA_RTC #define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
...@@ -140,10 +151,12 @@ ...@@ -140,10 +151,12 @@
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_SROMC EXYNOS4_PA_SROMC #define S5P_PA_SROMC EXYNOS4_PA_SROMC
#define S5P_PA_MFC EXYNOS4_PA_MFC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON #define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER #define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define S5P_PA_EHCI EXYNOS4_PA_EHCI #define S5P_PA_EHCI EXYNOS4_PA_EHCI
......
arch/arm/mach-exynos4/include/mach/pm-core.h
浏览文件 @ 1e09939b
...@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, ...@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
{ {
/* nothing here yet */ /* nothing here yet */
} }
static inline void s3c_pm_restored_gpios(void)
{
/* nothing here yet */
}
static inline void s3c_pm_saved_gpios(void)
{
/* nothing here yet */
}
arch/arm/mach-exynos4/include/mach/pmu.h 0 → 100644
浏览文件 @ 1e09939b
/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4210 - PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PMU_H
#define __ASM_ARCH_PMU_H __FILE__
enum sys_powerdown {
SYS_AFTR,
SYS_LPA,
SYS_SLEEP,
NUM_SYS_POWERDOWN,
};
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
#endif /* __ASM_ARCH_PMU_H */
arch/arm/mach-exynos4/include/mach/regs-audss.h 0 → 100644
浏览文件 @ 1e09939b
/* arch/arm/mach-exynos4/include/mach/regs-audss.h
*
* Copyright (c) 2011 Samsung Electronics
* http://www.samsung.com
*
* Exynos4 Audio SubSystem clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_AUDSS_H
#define __PLAT_REGS_AUDSS_H __FILE__
#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
#endif /* _PLAT_REGS_AUDSS_H */
arch/arm/mach-exynos4/include/mach/regs-clock.h
浏览文件 @ 1e09939b
...@@ -25,6 +25,9 @@ ...@@ -25,6 +25,9 @@
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) #define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) #define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) #define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
...@@ -33,7 +36,9 @@ ...@@ -33,7 +36,9 @@
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) #define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
...@@ -61,6 +66,7 @@ ...@@ -61,6 +66,7 @@
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
...@@ -120,6 +126,12 @@ ...@@ -120,6 +126,12 @@
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) #define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) #define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
#define S5P_EPLLCON0_ENABLE_SHIFT (31)
#define S5P_EPLLCON0_LOCKED_SHIFT (29)
#define S5P_VPLLCON0_ENABLE_SHIFT (31)
#define S5P_VPLLCON0_LOCKED_SHIFT (29)
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) #define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) #define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
......
arch/arm/mach-exynos4/include/mach/regs-pmu.h
浏览文件 @ 1e09939b
...@@ -158,6 +158,7 @@ ...@@ -158,6 +158,7 @@
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 #define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
#define S5P_CORE_LOCAL_PWR_EN 0x3
#define S5P_INT_LOCAL_PWR_EN 0x7 #define S5P_INT_LOCAL_PWR_EN 0x7
#define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_SLEEP 0x00000BAD
......
arch/arm/mach-exynos4/mach-nuri.c
浏览文件 @ 1e09939b
此差异已折叠。
arch/arm/mach-exynos4/mach-smdkc210.c
浏览文件 @ 1e09939b
...@@ -9,7 +9,9 @@ ...@@ -9,7 +9,9 @@
*/ */
#include <linux/serial_core.h> #include <linux/serial_core.h>
#include <linux/delay.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/lcd.h>
#include <linux/mmc/host.h> #include <linux/mmc/host.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/smsc911x.h> #include <linux/smsc911x.h>
...@@ -19,11 +21,15 @@ ...@@ -19,11 +21,15 @@
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <video/platform_lcd.h>
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
#include <plat/regs-srom.h> #include <plat/regs-srom.h>
#include <plat/regs-fb-v4.h>
#include <plat/exynos4.h> #include <plat/exynos4.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/fb.h>
#include <plat/sdhci.h> #include <plat/sdhci.h>
#include <plat/iic.h> #include <plat/iic.h>
#include <plat/pd.h> #include <plat/pd.h>
...@@ -111,6 +117,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = { ...@@ -111,6 +117,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
}; };
static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
unsigned int power)
{
if (power) {
#if !defined(CONFIG_BACKLIGHT_PWM)
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
gpio_free(EXYNOS4_GPD0(1));
#endif
/* fire nRESET on power up */
gpio_request(EXYNOS4_GPX0(6), "GPX0");
gpio_direction_output(EXYNOS4_GPX0(6), 1);
mdelay(100);
gpio_set_value(EXYNOS4_GPX0(6), 0);
mdelay(10);
gpio_set_value(EXYNOS4_GPX0(6), 1);
mdelay(10);
gpio_free(EXYNOS4_GPX0(6));
} else {
#if !defined(CONFIG_BACKLIGHT_PWM)
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
gpio_free(EXYNOS4_GPD0(1));
#endif
}
}
static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
.set_power = lcd_lte480wv_set_power,
};
static struct platform_device smdkc210_lcd_lte480wv = {
.name = "platform-lcd",
.dev.parent = &s5p_device_fimd0.dev,
.dev.platform_data = &smdkc210_lcd_lte480wv_data,
};
static struct s3c_fb_pd_win smdkc210_fb_win0 = {
.win_mode = {
.left_margin = 13,
.right_margin = 8,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 24,
};
static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
.win[0] = &smdkc210_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
static struct resource smdkc210_smsc911x_resources[] = { static struct resource smdkc210_smsc911x_resources[] = {
[0] = { [0] = {
.start = EXYNOS4_PA_SROM_BANK(1), .start = EXYNOS4_PA_SROM_BANK(1),
...@@ -165,6 +232,8 @@ static struct platform_device *smdkc210_devices[] __initdata = { ...@@ -165,6 +232,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
&exynos4_device_pd[PD_GPS], &exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu, &exynos4_device_sysmmu,
&samsung_asoc_dma, &samsung_asoc_dma,
&s5p_device_fimd0,
&smdkc210_lcd_lte480wv,
&smdkc210_smsc911x, &smdkc210_smsc911x,
}; };
...@@ -210,6 +279,8 @@ static void __init smdkc210_machine_init(void) ...@@ -210,6 +279,8 @@ static void __init smdkc210_machine_init(void)
s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
} }
......
arch/arm/mach-exynos4/mach-smdkv310.c
浏览文件 @ 1e09939b
...@@ -181,9 +181,12 @@ static struct platform_device *smdkv310_devices[] __initdata = { ...@@ -181,9 +181,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&exynos4_device_pd[PD_CAM], &exynos4_device_pd[PD_CAM],
&exynos4_device_pd[PD_TV], &exynos4_device_pd[PD_TV],
&exynos4_device_pd[PD_GPS], &exynos4_device_pd[PD_GPS],
&exynos4_device_spdif,
&exynos4_device_sysmmu, &exynos4_device_sysmmu,
&samsung_asoc_dma, &samsung_asoc_dma,
&samsung_asoc_idma,
&smdkv310_smsc911x, &smdkv310_smsc911x,
&exynos4_device_ahci,
}; };
static void __init smdkv310_smsc911x_init(void) static void __init smdkv310_smsc911x_init(void)
......
arch/arm/mach-exynos4/mach-universal_c210.c
浏览文件 @ 1e09939b
...@@ -18,6 +18,9 @@ ...@@ -18,6 +18,9 @@
#include <linux/regulator/fixed.h> #include <linux/regulator/fixed.h>
#include <linux/regulator/max8952.h> #include <linux/regulator/max8952.h>
#include <linux/mmc/host.h> #include <linux/mmc/host.h>
#include <linux/i2c-gpio.h>
#include <linux/i2c/mcs.h>
#include <linux/i2c/atmel_mxt_ts.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
...@@ -27,7 +30,10 @@ ...@@ -27,7 +30,10 @@
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/iic.h> #include <plat/iic.h>
#include <plat/gpio-cfg.h>
#include <plat/mfc.h>
#include <plat/sdhci.h> #include <plat/sdhci.h>
#include <plat/pd.h>
#include <mach/map.h> #include <mach/map.h>
...@@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = { ...@@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
}, },
}; };
/* I2C3 (TSP) */
static struct mxt_platform_data qt602240_platform_data = {
.x_line = 19,
.y_line = 11,
.x_size = 800,
.y_size = 480,
.blen = 0x11,
.threshold = 0x28,
.voltage = 2800000, /* 2.8V */
.orient = MXT_DIAGONAL,
};
static struct i2c_board_info i2c3_devs[] __initdata = {
{
I2C_BOARD_INFO("qt602240_ts", 0x4a),
.platform_data = &qt602240_platform_data,
},
};
static void __init universal_tsp_init(void)
{
int gpio;
/* TSP_LDO_ON: XMDMADDR_11 */
gpio = EXYNOS4_GPE2(3);
gpio_request(gpio, "TSP_LDO_ON");
gpio_direction_output(gpio, 1);
gpio_export(gpio, 0);
/* TSP_INT: XMDMADDR_7 */
gpio = EXYNOS4_GPE1(7);
gpio_request(gpio, "TSP_INT");
s5p_register_gpio_interrupt(gpio);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
i2c3_devs[0].irq = gpio_to_irq(gpio);
}
/* GPIO I2C 12 (3 Touchkey) */
static uint32_t touchkey_keymap[] = {
/* MCS_KEY_MAP(value, keycode) */
MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
};
static struct mcs_platform_data touchkey_data = {
.keymap = touchkey_keymap,
.keymap_size = ARRAY_SIZE(touchkey_keymap),
.key_maxval = 2,
};
/* GPIO I2C 3_TOUCH 2.8V */
#define I2C_GPIO_BUS_12 12
static struct i2c_gpio_platform_data i2c_gpio12_data = {
.sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
.scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
};
static struct platform_device i2c_gpio12 = {
.name = "i2c-gpio",
.id = I2C_GPIO_BUS_12,
.dev = {
.platform_data = &i2c_gpio12_data,
},
};
static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
{
I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
.platform_data = &touchkey_data,
},
};
static void __init universal_touchkey_init(void)
{
int gpio;
gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
gpio_request(gpio, "3_TOUCH_INT");
s5p_register_gpio_interrupt(gpio);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
gpio_request(gpio, "3_TOUCH_EN");
gpio_direction_output(gpio, 1);
}
/* GPIO KEYS */ /* GPIO KEYS */
static struct gpio_keys_button universal_gpio_keys_tables[] = { static struct gpio_keys_button universal_gpio_keys_tables[] = {
{ {
...@@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = { ...@@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
static struct platform_device *universal_devices[] __initdata = { static struct platform_device *universal_devices[] __initdata = {
/* Samsung Platform Devices */ /* Samsung Platform Devices */
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc3,
&mmc0_fixed_voltage, &mmc0_fixed_voltage,
&s3c_device_hsmmc0, &s3c_device_hsmmc0,
&s3c_device_hsmmc2, &s3c_device_hsmmc2,
&s3c_device_hsmmc3, &s3c_device_hsmmc3,
&s3c_device_i2c3,
&s3c_device_i2c5, &s3c_device_i2c5,
/* Universal Devices */ /* Universal Devices */
&i2c_gpio12,
&universal_gpio_keys, &universal_gpio_keys,
&s5p_device_onenand, &s5p_device_onenand,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
}; };
static void __init universal_map_io(void) static void __init universal_map_io(void)
...@@ -626,6 +732,11 @@ static void __init universal_map_io(void) ...@@ -626,6 +732,11 @@ static void __init universal_map_io(void)
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
} }
static void __init universal_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init universal_machine_init(void) static void __init universal_machine_init(void)
{ {
universal_sdhci_init(); universal_sdhci_init();
...@@ -633,11 +744,20 @@ static void __init universal_machine_init(void) ...@@ -633,11 +744,20 @@ static void __init universal_machine_init(void)
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
universal_tsp_init();
s3c_i2c3_set_platdata(NULL);
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
s3c_i2c5_set_platdata(NULL); s3c_i2c5_set_platdata(NULL);
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
universal_touchkey_init();
i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
ARRAY_SIZE(i2c_gpio12_devs));
/* Last */ /* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
} }
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
...@@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") ...@@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
.map_io = universal_map_io, .map_io = universal_map_io,
.init_machine = universal_machine_init, .init_machine = universal_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.reserve = &universal_reserve,
MACHINE_END MACHINE_END
arch/arm/mach-exynos4/mct.c
浏览文件 @ 1e09939b
...@@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt) ...@@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
} else { } else {
mct_tick1_event_irq.dev_id = &mct_tick[cpu]; mct_tick1_event_irq.dev_id = &mct_tick[cpu];
irq_set_affinity(IRQ_MCT1, cpumask_of(1));
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
} }
} }
......
arch/arm/mach-exynos4/platsmp.c
浏览文件 @ 1e09939b
...@@ -28,9 +28,12 @@ ...@@ -28,9 +28,12 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/regs-clock.h> #include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
extern void exynos4_secondary_startup(void); extern void exynos4_secondary_startup(void);
#define CPU1_BOOT_REG S5P_VA_SYSRAM
/* /*
* control for which core is the next to come out of the secondary * control for which core is the next to come out of the secondary
* boot "holding pen" * boot "holding pen"
...@@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void) ...@@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock); static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos4_gic_secondary_init(void)
{
void __iomem *dist_base = S5P_VA_GIC_DIST +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
void __iomem *cpu_base = S5P_VA_GIC_CPU +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
int i;
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
__raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
__raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
/*
* Set priority on PPI and SGI interrupts
*/
for (i = 0; i < 32; i += 4)
__raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
__raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
__raw_writel(1, cpu_base + GIC_CPU_CTRL);
}
void __cpuinit platform_secondary_init(unsigned int cpu) void __cpuinit platform_secondary_init(unsigned int cpu)
{ {
/* /*
...@@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) ...@@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled * core (e.g. timer irq), then they will not have been enabled
* for us: do so * for us: do so
*/ */
gic_secondary_init(0); exynos4_gic_secondary_init();
/* /*
* let the primary processor know we're out of the * let the primary processor know we're out of the
...@@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/ */
write_pen_release(cpu); write_pen_release(cpu);
if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
S5P_ARM_CORE1_CONFIGURATION);
timeout = 10;
/* wait max 10 ms until cpu1 is on */
while ((__raw_readl(S5P_ARM_CORE1_STATUS)
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
mdelay(1);
}
if (timeout == 0) {
printk(KERN_ERR "cpu1 power enable failed");
spin_unlock(&boot_lock);
return -ETIMEDOUT;
}
}
/* /*
* Send the secondary CPU a soft interrupt, thereby causing * Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register, * the boot monitor to read the system wide flags register,
* and branch to the address found there. * and branch to the address found there.
*/ */
gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
smp_rmb(); smp_rmb();
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
CPU1_BOOT_REG);
gic_raise_softirq(cpumask_of(cpu), 1);
if (pen_release == -1) if (pen_release == -1)
break; break;
......
arch/arm/mach-exynos4/pm.c
浏览文件 @ 1e09939b
...@@ -18,92 +18,23 @@ ...@@ -18,92 +18,23 @@
#include <linux/suspend.h> #include <linux/suspend.h>
#include <linux/syscore_ops.h> #include <linux/syscore_ops.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-l2x0.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/pm.h> #include <plat/pm.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>
#include <mach/regs-irq.h> #include <mach/regs-irq.h>
#include <mach/regs-gpio.h> #include <mach/regs-gpio.h>
#include <mach/regs-clock.h> #include <mach/regs-clock.h>
#include <mach/regs-pmu.h> #include <mach/regs-pmu.h>
#include <mach/pm-core.h> #include <mach/pm-core.h>
#include <mach/pmu.h>
static struct sleep_save exynos4_sleep[] = {
{ .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
{ .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
{ .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
{ .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
{ .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
{ .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
{ .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
{ .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
{ .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
{ .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
{ .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
{ .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
{ .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
{ .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
{ .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
{ .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
{ .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
{ .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
};
static struct sleep_save exynos4_set_clksrc[] = { static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
...@@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = { ...@@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
}; };
static struct sleep_save exynos4_epll_save[] = {
SAVE_ITEM(S5P_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1),
};
static struct sleep_save exynos4_vpll_save[] = {
SAVE_ITEM(S5P_VPLL_CON0),
SAVE_ITEM(S5P_VPLL_CON1),
};
static struct sleep_save exynos4_core_save[] = { static struct sleep_save exynos4_core_save[] = {
/* CMU side */ /* CMU side */
SAVE_ITEM(S5P_CLKDIV_LEFTBUS), SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
SAVE_ITEM(S5P_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1),
SAVE_ITEM(S5P_VPLL_CON0),
SAVE_ITEM(S5P_VPLL_CON1),
SAVE_ITEM(S5P_CLKSRC_TOP0), SAVE_ITEM(S5P_CLKSRC_TOP0),
SAVE_ITEM(S5P_CLKSRC_TOP1), SAVE_ITEM(S5P_CLKSRC_TOP1),
SAVE_ITEM(S5P_CLKSRC_CAM), SAVE_ITEM(S5P_CLKSRC_CAM),
SAVE_ITEM(S5P_CLKSRC_TV),
SAVE_ITEM(S5P_CLKSRC_MFC), SAVE_ITEM(S5P_CLKSRC_MFC),
SAVE_ITEM(S5P_CLKSRC_G3D),
SAVE_ITEM(S5P_CLKSRC_IMAGE), SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKSRC_LCD0), SAVE_ITEM(S5P_CLKSRC_LCD0),
SAVE_ITEM(S5P_CLKSRC_LCD1), SAVE_ITEM(S5P_CLKSRC_LCD1),
...@@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = { ...@@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKDIV_PERIL4), SAVE_ITEM(S5P_CLKDIV_PERIL4),
SAVE_ITEM(S5P_CLKDIV_PERIL5), SAVE_ITEM(S5P_CLKDIV_PERIL5),
SAVE_ITEM(S5P_CLKDIV_TOP), SAVE_ITEM(S5P_CLKDIV_TOP),
SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
SAVE_ITEM(S5P_CLKSRC_MASK_CAM), SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
SAVE_ITEM(S5P_CLKSRC_MASK_TV), SAVE_ITEM(S5P_CLKSRC_MASK_TV),
SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
...@@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = { ...@@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
SAVE_ITEM(S5P_CLKDIV2_RATIO),
SAVE_ITEM(S5P_CLKGATE_SCLKCAM), SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
SAVE_ITEM(S5P_CLKGATE_IP_CAM), SAVE_ITEM(S5P_CLKGATE_IP_CAM),
SAVE_ITEM(S5P_CLKGATE_IP_TV), SAVE_ITEM(S5P_CLKGATE_IP_TV),
...@@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = { ...@@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKGATE_IP_DMC), SAVE_ITEM(S5P_CLKGATE_IP_DMC),
SAVE_ITEM(S5P_CLKSRC_CPU), SAVE_ITEM(S5P_CLKSRC_CPU),
SAVE_ITEM(S5P_CLKDIV_CPU), SAVE_ITEM(S5P_CLKDIV_CPU),
SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
SAVE_ITEM(S5P_CLKGATE_SCLKCPU), SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
SAVE_ITEM(S5P_CLKGATE_IP_CPU), SAVE_ITEM(S5P_CLKGATE_IP_CPU),
/* GIC side */ /* GIC side */
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
...@@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = { ...@@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
/* SROM side */
SAVE_ITEM(S5P_SROM_BW),
SAVE_ITEM(S5P_SROM_BC0),
SAVE_ITEM(S5P_SROM_BC1),
SAVE_ITEM(S5P_SROM_BC2),
SAVE_ITEM(S5P_SROM_BC3),
}; };
static struct sleep_save exynos4_l2cc_save[] = { static struct sleep_save exynos4_l2cc_save[] = {
...@@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = { ...@@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = {
SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
}; };
void exynos4_cpu_suspend(void) /* For Cortex-A9 Diagnostic and Power control register */
{ static unsigned int save_arm_register[2];
unsigned long tmp;
unsigned long mask = 0xFFFFFFFF;
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* Setting Central Sequence option Register */
tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
tmp &= ~(S5P_USE_MASK);
tmp |= S5P_USE_STANDBY_WFI0;
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
/* Clear all interrupt pending to avoid early wakeup */
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
/* Disable all interrupt */
__raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
__raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
void exynos4_cpu_suspend(unsigned long arg)
{
outer_flush_all(); outer_flush_all();
/* issue the standby signal into the pm unit. */ /* issue the standby signal into the pm unit. */
...@@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void) ...@@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void)
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
tmp = __raw_readl(S5P_INFORM1); tmp = __raw_readl(S5P_INFORM1);
/* Set value of power down register for sleep mode */ /* Set value of power down register for sleep mode */
s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep)); exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */ /* ensure at least INFORM0 has the resume address */
...@@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base) ...@@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
flush_cache_all(); flush_cache_all();
} }
static unsigned long pll_base_rate;
static void exynos4_restore_pll(void)
{
unsigned long pll_con, locktime, lockcnt;
unsigned long pll_in_rate;
unsigned int p_div, epll_wait = 0, vpll_wait = 0;
if (pll_base_rate == 0)
return;
pll_in_rate = pll_base_rate;
/* EPLL */
pll_con = exynos4_epll_save[0].val;
if (pll_con & (1 << 31)) {
pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
pll_in_rate /= 1000000;
locktime = (3000 / pll_in_rate) * p_div;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
__raw_writel(lockcnt, S5P_EPLL_LOCK);
s3c_pm_do_restore_core(exynos4_epll_save,
ARRAY_SIZE(exynos4_epll_save));
epll_wait = 1;
}
pll_in_rate = pll_base_rate;
/* VPLL */
pll_con = exynos4_vpll_save[0].val;
if (pll_con & (1 << 31)) {
pll_in_rate /= 1000000;
/* 750us */
locktime = 750;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
__raw_writel(lockcnt, S5P_VPLL_LOCK);
s3c_pm_do_restore_core(exynos4_vpll_save,
ARRAY_SIZE(exynos4_vpll_save));
vpll_wait = 1;
}
/* Wait PLL locking */
do {
if (epll_wait) {
pll_con = __raw_readl(S5P_EPLL_CON0);
if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
epll_wait = 0;
}
if (vpll_wait) {
pll_con = __raw_readl(S5P_VPLL_CON0);
if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
vpll_wait = 0;
}
} while (epll_wait || vpll_wait);
}
static struct sysdev_driver exynos4_pm_driver = { static struct sysdev_driver exynos4_pm_driver = {
.add = exynos4_pm_add, .add = exynos4_pm_add,
}; };
static __init int exynos4_pm_drvinit(void) static __init int exynos4_pm_drvinit(void)
{ {
struct clk *pll_base;
unsigned int tmp; unsigned int tmp;
s3c_pm_init(); s3c_pm_init();
...@@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void) ...@@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void)
tmp |= ((0xFF << 8) | (0x1F << 1)); tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK); __raw_writel(tmp, S5P_WAKEUP_MASK);
pll_base = clk_get(NULL, "xtal");
if (!IS_ERR(pll_base)) {
pll_base_rate = clk_get_rate(pll_base);
clk_put(pll_base);
}
return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
} }
arch_initcall(exynos4_pm_drvinit); arch_initcall(exynos4_pm_drvinit);
static int exynos4_pm_suspend(void)
{
unsigned long tmp;
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* Save Power control register */
asm ("mrc p15, 0, %0, c15, c0, 0"
: "=r" (tmp) : : "cc");
save_arm_register[0] = tmp;
/* Save Diagnostic register */
asm ("mrc p15, 0, %0, c15, c0, 1"
: "=r" (tmp) : : "cc");
save_arm_register[1] = tmp;
return 0;
}
static void exynos4_pm_resume(void) static void exynos4_pm_resume(void)
{ {
unsigned long tmp;
/*
* If PMU failed while entering sleep mode, WFI will be
* ignored by PMU and then exiting cpu_do_idle().
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* No need to perform below restore code */
goto early_wakeup;
}
/* Restore Power control register */
tmp = save_arm_register[0];
asm volatile ("mcr p15, 0, %0, c15, c0, 0"
: : "r" (tmp)
: "cc");
/* Restore Diagnostic register */
tmp = save_arm_register[1];
asm volatile ("mcr p15, 0, %0, c15, c0, 1"
: : "r" (tmp)
: "cc");
/* For release retention */ /* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
...@@ -407,6 +458,8 @@ static void exynos4_pm_resume(void) ...@@ -407,6 +458,8 @@ static void exynos4_pm_resume(void)
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
exynos4_restore_pll();
exynos4_scu_enable(S5P_VA_SCU); exynos4_scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
...@@ -415,9 +468,13 @@ static void exynos4_pm_resume(void) ...@@ -415,9 +468,13 @@ static void exynos4_pm_resume(void)
/* enable L2X0*/ /* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif #endif
early_wakeup:
return;
} }
static struct syscore_ops exynos4_pm_syscore_ops = { static struct syscore_ops exynos4_pm_syscore_ops = {
.suspend = exynos4_pm_suspend,
.resume = exynos4_pm_resume, .resume = exynos4_pm_resume,
}; };
......
arch/arm/mach-exynos4/pmu.c 0 → 100644
浏览文件 @ 1e09939b
/* linux/arch/arm/mach-exynos4/pmu.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4210 - CPU PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <mach/regs-clock.h>
#include <mach/pmu.h>
static void __iomem *sys_powerdown_reg[] = {
S5P_ARM_CORE0_LOWPWR,
S5P_DIS_IRQ_CORE0,
S5P_DIS_IRQ_CENTRAL0,
S5P_ARM_CORE1_LOWPWR,
S5P_DIS_IRQ_CORE1,
S5P_DIS_IRQ_CENTRAL1,
S5P_ARM_COMMON_LOWPWR,
S5P_L2_0_LOWPWR,
S5P_L2_1_LOWPWR,
S5P_CMU_ACLKSTOP_LOWPWR,
S5P_CMU_SCLKSTOP_LOWPWR,
S5P_CMU_RESET_LOWPWR,
S5P_APLL_SYSCLK_LOWPWR,
S5P_MPLL_SYSCLK_LOWPWR,
S5P_VPLL_SYSCLK_LOWPWR,
S5P_EPLL_SYSCLK_LOWPWR,
S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
S5P_CMU_RESET_GPSALIVE_LOWPWR,
S5P_CMU_CLKSTOP_CAM_LOWPWR,
S5P_CMU_CLKSTOP_TV_LOWPWR,
S5P_CMU_CLKSTOP_MFC_LOWPWR,
S5P_CMU_CLKSTOP_G3D_LOWPWR,
S5P_CMU_CLKSTOP_LCD0_LOWPWR,
S5P_CMU_CLKSTOP_LCD1_LOWPWR,
S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
S5P_CMU_CLKSTOP_GPS_LOWPWR,
S5P_CMU_RESET_CAM_LOWPWR,
S5P_CMU_RESET_TV_LOWPWR,
S5P_CMU_RESET_MFC_LOWPWR,
S5P_CMU_RESET_G3D_LOWPWR,
S5P_CMU_RESET_LCD0_LOWPWR,
S5P_CMU_RESET_LCD1_LOWPWR,
S5P_CMU_RESET_MAUDIO_LOWPWR,
S5P_CMU_RESET_GPS_LOWPWR,
S5P_TOP_BUS_LOWPWR,
S5P_TOP_RETENTION_LOWPWR,
S5P_TOP_PWR_LOWPWR,
S5P_LOGIC_RESET_LOWPWR,
S5P_ONENAND_MEM_LOWPWR,
S5P_MODIMIF_MEM_LOWPWR,
S5P_G2D_ACP_MEM_LOWPWR,
S5P_USBOTG_MEM_LOWPWR,
S5P_HSMMC_MEM_LOWPWR,
S5P_CSSYS_MEM_LOWPWR,
S5P_SECSS_MEM_LOWPWR,
S5P_PCIE_MEM_LOWPWR,
S5P_SATA_MEM_LOWPWR,
S5P_PAD_RETENTION_DRAM_LOWPWR,
S5P_PAD_RETENTION_MAUDIO_LOWPWR,
S5P_PAD_RETENTION_GPIO_LOWPWR,
S5P_PAD_RETENTION_UART_LOWPWR,
S5P_PAD_RETENTION_MMCA_LOWPWR,
S5P_PAD_RETENTION_MMCB_LOWPWR,
S5P_PAD_RETENTION_EBIA_LOWPWR,
S5P_PAD_RETENTION_EBIB_LOWPWR,
S5P_PAD_RETENTION_ISOLATION_LOWPWR,
S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
S5P_XUSBXTI_LOWPWR,
S5P_XXTI_LOWPWR,
S5P_EXT_REGULATOR_LOWPWR,
S5P_GPIO_MODE_LOWPWR,
S5P_GPIO_MODE_MAUDIO_LOWPWR,
S5P_CAM_LOWPWR,
S5P_TV_LOWPWR,
S5P_MFC_LOWPWR,
S5P_G3D_LOWPWR,
S5P_LCD0_LOWPWR,
S5P_LCD1_LOWPWR,
S5P_MAUDIO_LOWPWR,
S5P_GPS_LOWPWR,
S5P_GPS_ALIVE_LOWPWR,
};
static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
/* { AFTR, LPA, SLEEP }*/
{ 0, 0, 2 }, /* ARM_CORE0 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
{ 0, 0, 2 }, /* ARM_CORE1 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
{ 0, 0, 2 }, /* ARM_COMMON */
{ 2, 2, 3 }, /* ARM_CPU_L2_0 */
{ 2, 2, 3 }, /* ARM_CPU_L2_1 */
{ 1, 0, 0 }, /* CMU_ACLKSTOP */
{ 1, 0, 0 }, /* CMU_SCLKSTOP */
{ 1, 1, 0 }, /* CMU_RESET */
{ 1, 0, 0 }, /* APLL_SYSCLK */
{ 1, 0, 0 }, /* MPLL_SYSCLK */
{ 1, 0, 0 }, /* VPLL_SYSCLK */
{ 1, 1, 0 }, /* EPLL_SYSCLK */
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
{ 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
{ 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
{ 1, 1, 0 }, /* CMU_CLKSTOP_TV */
{ 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
{ 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
{ 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
{ 1, 1, 0 }, /* CMU_RESET_CAM */
{ 1, 1, 0 }, /* CMU_RESET_TV */
{ 1, 1, 0 }, /* CMU_RESET_MFC */
{ 1, 1, 0 }, /* CMU_RESET_G3D */
{ 1, 1, 0 }, /* CMU_RESET_LCD0 */
{ 1, 1, 0 }, /* CMU_RESET_LCD1 */
{ 1, 1, 0 }, /* CMU_RESET_MAUDIO */
{ 1, 1, 0 }, /* CMU_RESET_GPS */
{ 3, 0, 0 }, /* TOP_BUS */
{ 1, 0, 1 }, /* TOP_RETENTION */
{ 3, 0, 3 }, /* TOP_PWR */
{ 1, 1, 0 }, /* LOGIC_RESET */
{ 3, 0, 0 }, /* ONENAND_MEM */
{ 3, 0, 0 }, /* MODIMIF_MEM */
{ 3, 0, 0 }, /* G2D_ACP_MEM */
{ 3, 0, 0 }, /* USBOTG_MEM */
{ 3, 0, 0 }, /* HSMMC_MEM */
{ 3, 0, 0 }, /* CSSYS_MEM */
{ 3, 0, 0 }, /* SECSS_MEM */
{ 3, 0, 0 }, /* PCIE_MEM */
{ 3, 0, 0 }, /* SATA_MEM */
{ 1, 0, 0 }, /* PAD_RETENTION_DRAM */
{ 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
{ 1, 0, 0 }, /* PAD_RETENTION_GPIO */
{ 1, 0, 0 }, /* PAD_RETENTION_UART */
{ 1, 0, 0 }, /* PAD_RETENTION_MMCA */
{ 1, 0, 0 }, /* PAD_RETENTION_MMCB */
{ 1, 0, 0 }, /* PAD_RETENTION_EBIA */
{ 1, 0, 0 }, /* PAD_RETENTION_EBIB */
{ 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
{ 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
{ 1, 1, 0 }, /* XUSBXTI */
{ 1, 1, 0 }, /* XXTI */
{ 1, 1, 0 }, /* EXT_REGULATOR */
{ 1, 0, 0 }, /* GPIO_MODE */
{ 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
{ 7, 0, 0 }, /* CAM */
{ 7, 0, 0 }, /* TV */
{ 7, 0, 0 }, /* MFC */
{ 7, 0, 0 }, /* G3D */
{ 7, 0, 0 }, /* LCD0 */
{ 7, 0, 0 }, /* LCD1 */
{ 7, 7, 0 }, /* MAUDIO */
{ 7, 0, 0 }, /* GPS */
{ 7, 0, 0 }, /* GPS_ALIVE */
};
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
for (; count > 0; count--)
__raw_writel(sys_powerdown_val[count - 1][mode],
sys_powerdown_reg[count - 1]);
}
arch/arm/mach-exynos4/setup-fimd0.c 0 → 100644
浏览文件 @ 1e09939b
/* linux/arch/arm/mach-exynos4/setup-fimd0.c
*
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Base Exynos4 FIMD 0 configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/fb.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-fb-v4.h>
#include <mach/map.h>
void exynos4_fimd0_gpio_setup_24bpp(void)
{
unsigned int reg;
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
/*
* Set DISPLAY_CONTROL register for Display path selection.
*
* DISPLAY_CONTROL[1:0]
* ---------------------
* 00 | MIE
* 01 | MDINE
* 10 | FIMD : selected
* 11 | FIMD
*/
reg = __raw_readl(S3C_VA_SYS + 0x0210);
reg |= (1 << 1);
__raw_writel(reg, S3C_VA_SYS + 0x0210);
}
arch/arm/mach-exynos4/time.c 已删除 100644 → 0
浏览文件 @ 4d09a938
/* linux/arch/arm/mach-exynos4/time.c
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 (and compatible) HRT support
* PWM 2/4 is used for this feature
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/platform_device.h>
#include <asm/smp_twd.h>
#include <mach/map.h>
#include <plat/regs-timer.h>
#include <asm/mach/time.h>
static unsigned long clock_count_per_tick;
static struct clk *tin2;
static struct clk *tin4;
static struct clk *tdiv2;
static struct clk *tdiv4;
static struct clk *timerclk;
static void exynos4_pwm_stop(unsigned int pwm_id)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
switch (pwm_id) {
case 2:
tcon &= ~S3C2410_TCON_T2START;
break;
case 4:
tcon &= ~S3C2410_TCON_T4START;
break;
default:
break;
}
__raw_writel(tcon, S3C2410_TCON);
}
static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
/* timers reload after counting zero, so reduce the count by 1 */
tcnt--;
/* ensure timer is stopped... */
switch (pwm_id) {
case 2:
tcon &= ~(0xf<<12);
tcon |= S3C2410_TCON_T2MANUALUPD;
__raw_writel(tcnt, S3C2410_TCNTB(2));
__raw_writel(tcnt, S3C2410_TCMPB(2));
__raw_writel(tcon, S3C2410_TCON);
break;
case 4:
tcon &= ~(7<<20);
tcon |= S3C2410_TCON_T4MANUALUPD;
__raw_writel(tcnt, S3C2410_TCNTB(4));
__raw_writel(tcnt, S3C2410_TCMPB(4));
__raw_writel(tcon, S3C2410_TCON);
break;
default:
break;
}
}
static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
switch (pwm_id) {
case 2:
tcon |= S3C2410_TCON_T2START;
tcon &= ~S3C2410_TCON_T2MANUALUPD;
if (periodic)
tcon |= S3C2410_TCON_T2RELOAD;
else
tcon &= ~S3C2410_TCON_T2RELOAD;
break;
case 4:
tcon |= S3C2410_TCON_T4START;
tcon &= ~S3C2410_TCON_T4MANUALUPD;
if (periodic)
tcon |= S3C2410_TCON_T4RELOAD;
else
tcon &= ~S3C2410_TCON_T4RELOAD;
break;
default:
break;
}
__raw_writel(tcon, S3C2410_TCON);
}
static int exynos4_pwm_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
exynos4_pwm_init(2, cycles);
exynos4_pwm_start(2, 0);
return 0;
}
static void exynos4_pwm_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
exynos4_pwm_stop(2);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
exynos4_pwm_init(2, clock_count_per_tick);
exynos4_pwm_start(2, 1);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static struct clock_event_device pwm_event_device = {
.name = "pwm_timer2",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.shift = 32,
.set_next_event = exynos4_pwm_set_next_event,
.set_mode = exynos4_pwm_set_mode,
};
irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
{
struct clock_event_device *evt = &pwm_event_device;
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction exynos4_clock_event_irq = {
.name = "pwm_timer2_irq",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = exynos4_clock_event_isr,
};
static void __init exynos4_clockevent_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
struct clk *tscaler;
pclk = clk_get_rate(timerclk);
/* configure clock tick */
tscaler = clk_get_parent(tdiv2);
clk_set_rate(tscaler, pclk / 2);
clk_set_rate(tdiv2, pclk / 2);
clk_set_parent(tin2, tdiv2);
clock_rate = clk_get_rate(tin2);
clock_count_per_tick = clock_rate / HZ;
pwm_event_device.mult =
div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
pwm_event_device.max_delta_ns =
clockevent_delta2ns(-1, &pwm_event_device);
pwm_event_device.min_delta_ns =
clockevent_delta2ns(1, &pwm_event_device);
pwm_event_device.cpumask = cpumask_of(0);
clockevents_register_device(&pwm_event_device);
setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
}
static cycle_t exynos4_pwm4_read(struct clocksource *cs)
{
return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
}
#ifdef CONFIG_PM
static void exynos4_pwm4_resume(struct clocksource *cs)
{
unsigned long pclk;
pclk = clk_get_rate(timerclk);
clk_set_rate(tdiv4, pclk / 2);
clk_set_parent(tin4, tdiv4);
exynos4_pwm_init(4, ~0);
exynos4_pwm_start(4, 1);
}
#endif
struct clocksource pwm_clocksource = {
.name = "pwm_timer4",
.rating = 250,
.read = exynos4_pwm4_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS ,
#ifdef CONFIG_PM
.resume = exynos4_pwm4_resume,
#endif
};
static void __init exynos4_clocksource_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
pclk = clk_get_rate(timerclk);
clk_set_rate(tdiv4, pclk / 2);
clk_set_parent(tin4, tdiv4);
clock_rate = clk_get_rate(tin4);
exynos4_pwm_init(4, ~0);
exynos4_pwm_start(4, 1);
if (clocksource_register_hz(&pwm_clocksource, clock_rate))
panic("%s: can't register clocksource\n", pwm_clocksource.name);
}
static void __init exynos4_timer_resources(void)
{
struct platform_device tmpdev;
tmpdev.dev.bus = &platform_bus_type;
timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk))
panic("failed to get timers clock for system timer");
clk_enable(timerclk);
tmpdev.id = 2;
tin2 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin2))
panic("failed to get pwm-tin2 clock for system timer");
tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
if (IS_ERR(tdiv2))
panic("failed to get pwm-tdiv2 clock for system timer");
clk_enable(tin2);
tmpdev.id = 4;
tin4 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin4))
panic("failed to get pwm-tin4 clock for system timer");
tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
if (IS_ERR(tdiv4))
panic("failed to get pwm-tdiv4 clock for system timer");
clk_enable(tin4);
}
static void __init exynos4_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
twd_base = S5P_VA_TWD;
#endif
exynos4_timer_resources();
exynos4_clockevent_init();
exynos4_clocksource_init();
}
struct sys_timer exynos4_timer = {
.init = exynos4_timer_init,
};
arch/arm/mach-s3c2410/include/mach/pm-core.h
浏览文件 @ 1e09939b
...@@ -62,3 +62,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, ...@@ -62,3 +62,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save) struct pm_uart_save *save)
{ {
} }
static inline void s3c_pm_restored_gpios(void) { }
static inline void s3c_pm_saved_gpios(void) { }
arch/arm/mach-s3c2412/clock.c
浏览文件 @ 1e09939b
...@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable) ...@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
static struct clk clk_erefclk = { static struct clk clk_erefclk = {
.name = "erefclk", .name = "erefclk",
.id = -1,
}; };
static struct clk clk_urefclk = { static struct clk clk_urefclk = {
.name = "urefclk", .name = "urefclk",
.id = -1,
}; };
static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
...@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) ...@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
static struct clk clk_usysclk = { static struct clk clk_usysclk = {
.name = "usysclk", .name = "usysclk",
.id = -1,
.parent = &clk_xtal, .parent = &clk_xtal,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_usysclk, .set_parent = s3c2412_setparent_usysclk,
...@@ -132,13 +129,11 @@ static struct clk clk_usysclk = { ...@@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
static struct clk clk_mrefclk = { static struct clk clk_mrefclk = {
.name = "mrefclk", .name = "mrefclk",
.parent = &clk_xtal, .parent = &clk_xtal,
.id = -1,
}; };
static struct clk clk_mdivclk = { static struct clk clk_mdivclk = {
.name = "mdivclk", .name = "mdivclk",
.parent = &clk_xtal, .parent = &clk_xtal,
.id = -1,
}; };
static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
...@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) ...@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
static struct clk clk_usbsrc = { static struct clk clk_usbsrc = {
.name = "usbsrc", .name = "usbsrc",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_usbsrc, .get_rate = s3c2412_getrate_usbsrc,
.set_rate = s3c2412_setrate_usbsrc, .set_rate = s3c2412_setrate_usbsrc,
...@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) ...@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
static struct clk clk_msysclk = { static struct clk clk_msysclk = {
.name = "msysclk", .name = "msysclk",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_msysclk, .set_parent = s3c2412_setparent_msysclk,
}, },
...@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) ...@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
static struct clk clk_armclk = { static struct clk clk_armclk = {
.name = "armclk", .name = "armclk",
.id = -1,
.parent = &clk_msysclk, .parent = &clk_msysclk,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_armclk, .set_parent = s3c2412_setparent_armclk,
...@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) ...@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
static struct clk clk_uart = { static struct clk clk_uart = {
.name = "uartclk", .name = "uartclk",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_uart, .get_rate = s3c2412_getrate_uart,
.set_rate = s3c2412_setrate_uart, .set_rate = s3c2412_setrate_uart,
...@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) ...@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
static struct clk clk_i2s = { static struct clk clk_i2s = {
.name = "i2sclk", .name = "i2sclk",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_i2s, .get_rate = s3c2412_getrate_i2s,
.set_rate = s3c2412_setrate_i2s, .set_rate = s3c2412_setrate_i2s,
...@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) ...@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
static struct clk clk_cam = { static struct clk clk_cam = {
.name = "camif-upll", /* same as 2440 name */ .name = "camif-upll", /* same as 2440 name */
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_cam, .get_rate = s3c2412_getrate_cam,
.set_rate = s3c2412_setrate_cam, .set_rate = s3c2412_setrate_cam,
...@@ -463,37 +452,31 @@ static struct clk clk_cam = { ...@@ -463,37 +452,31 @@ static struct clk clk_cam = {
static struct clk init_clocks_disable[] = { static struct clk init_clocks_disable[] = {
{ {
.name = "nand", .name = "nand",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_NAND, .ctrlbit = S3C2412_CLKCON_NAND,
}, { }, {
.name = "sdi", .name = "sdi",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SDI, .ctrlbit = S3C2412_CLKCON_SDI,
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_ADC, .ctrlbit = S3C2412_CLKCON_ADC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIC, .ctrlbit = S3C2412_CLKCON_IIC,
}, { }, {
.name = "iis", .name = "iis",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIS, .ctrlbit = S3C2412_CLKCON_IIS,
}, { }, {
.name = "spi", .name = "spi",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SPI, .ctrlbit = S3C2412_CLKCON_SPI,
...@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = { ...@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "dma", .name = "dma",
.id = 0,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA0, .ctrlbit = S3C2412_CLKCON_DMA0,
}, { }, {
.name = "dma", .name = "dma",
.id = 1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA1, .ctrlbit = S3C2412_CLKCON_DMA1,
}, { }, {
.name = "dma", .name = "dma",
.id = 2,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA2, .ctrlbit = S3C2412_CLKCON_DMA2,
}, { }, {
.name = "dma", .name = "dma",
.id = 3,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA3, .ctrlbit = S3C2412_CLKCON_DMA3,
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_LCDC, .ctrlbit = S3C2412_CLKCON_LCDC,
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_GPIO, .ctrlbit = S3C2412_CLKCON_GPIO,
}, { }, {
.name = "usb-host", .name = "usb-host",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBH, .ctrlbit = S3C2412_CLKCON_USBH,
}, { }, {
.name = "usb-device", .name = "usb-device",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBD, .ctrlbit = S3C2412_CLKCON_USBD,
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_PWMT, .ctrlbit = S3C2412_CLKCON_PWMT,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c2412-uart.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART0, .ctrlbit = S3C2412_CLKCON_UART0,
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c2412-uart.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART1, .ctrlbit = S3C2412_CLKCON_UART1,
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c2412-uart.2",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART2, .ctrlbit = S3C2412_CLKCON_UART2,
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_RTC, .ctrlbit = S3C2412_CLKCON_RTC,
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = 0, .ctrlbit = 0,
}, { }, {
.name = "usb-bus-gadget", .name = "usb-bus-gadget",
.id = -1,
.parent = &clk_usb_bus, .parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_DEV48, .ctrlbit = S3C2412_CLKCON_USB_DEV48,
}, { }, {
.name = "usb-bus-host", .name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus, .parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_HOST48, .ctrlbit = S3C2412_CLKCON_USB_HOST48,
......
arch/arm/mach-s3c2416/clock.c
浏览文件 @ 1e09939b
...@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = { ...@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
[0] = { [0] = {
.clk = { .clk = {
.name = "hsmmc-div", .name = "hsmmc-div",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
...@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = { ...@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
[1] = { [1] = {
.clk = { .clk = {
.name = "hsmmc-div", .name = "hsmmc-div",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
...@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = { ...@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
static struct clksrc_clk hsmmc_mux[] = { static struct clksrc_clk hsmmc_mux[] = {
[0] = { [0] = {
.clk = { .clk = {
.id = 0,
.name = "hsmmc-if", .name = "hsmmc-if",
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
}, },
...@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = { ...@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
}, },
[1] = { [1] = {
.clk = { .clk = {
.id = 1,
.name = "hsmmc-if", .name = "hsmmc-if",
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
}, },
...@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = { ...@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {
static struct clk hsmmc0_clk = { static struct clk hsmmc0_clk = {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2416_HCLKCON_HSMMC0, .ctrlbit = S3C2416_HCLKCON_HSMMC0,
......
arch/arm/mach-s3c2440/clock.c
浏览文件 @ 1e09939b
...@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) ...@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
static struct clk s3c2440_clk_cam = { static struct clk s3c2440_clk_cam = {
.name = "camif", .name = "camif",
.id = -1,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA, .ctrlbit = S3C2440_CLKCON_CAMERA,
}; };
static struct clk s3c2440_clk_cam_upll = { static struct clk s3c2440_clk_cam_upll = {
.name = "camif-upll", .name = "camif-upll",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.set_rate = s3c2440_camif_upll_setrate, .set_rate = s3c2440_camif_upll_setrate,
.round_rate = s3c2440_camif_upll_round, .round_rate = s3c2440_camif_upll_round,
...@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = { ...@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {
static struct clk s3c2440_clk_ac97 = { static struct clk s3c2440_clk_ac97 = {
.name = "ac97", .name = "ac97",
.id = -1,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA, .ctrlbit = S3C2440_CLKCON_CAMERA,
}; };
......
arch/arm/mach-s3c2443/clock.c
浏览文件 @ 1e09939b
...@@ -59,7 +59,6 @@ ...@@ -59,7 +59,6 @@
static struct clk clk_i2s_ext = { static struct clk clk_i2s_ext = {
.name = "i2s-ext", .name = "i2s-ext",
.id = -1,
}; };
/* armdiv /* armdiv
...@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) ...@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
static struct clk clk_armdiv = { static struct clk clk_armdiv = {
.name = "armdiv", .name = "armdiv",
.id = -1,
.parent = &clk_msysclk.clk, .parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.round_rate = s3c2443_armclk_roundrate, .round_rate = s3c2443_armclk_roundrate,
...@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = { ...@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
static struct clksrc_clk clk_arm = { static struct clksrc_clk clk_arm = {
.clk = { .clk = {
.name = "armclk", .name = "armclk",
.id = -1,
}, },
.sources = &(struct clksrc_sources) { .sources = &(struct clksrc_sources) {
.sources = clk_arm_sources, .sources = clk_arm_sources,
...@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = { ...@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
static struct clksrc_clk clk_hsspi = { static struct clksrc_clk clk_hsspi = {
.clk = { .clk = {
.name = "hsspi", .name = "hsspi",
.id = -1,
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_HSSPICLK, .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
...@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = { ...@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
static struct clksrc_clk clk_hsmmc_div = { static struct clksrc_clk clk_hsmmc_div = {
.clk = { .clk = {
.name = "hsmmc-div", .name = "hsmmc-div",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
...@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable) ...@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
static struct clk clk_hsmmc = { static struct clk clk_hsmmc = {
.name = "hsmmc-if", .name = "hsmmc-if",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_hsmmc_div.clk, .parent = &clk_hsmmc_div.clk,
.enable = s3c2443_enable_hsmmc, .enable = s3c2443_enable_hsmmc,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
...@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = { ...@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
static struct clksrc_clk clk_i2s_eplldiv = { static struct clksrc_clk clk_i2s_eplldiv = {
.clk = { .clk = {
.name = "i2s-eplldiv", .name = "i2s-eplldiv",
.id = -1,
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
...@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = { ...@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
static struct clksrc_clk clk_i2s = { static struct clksrc_clk clk_i2s = {
.clk = { .clk = {
.name = "i2s-if", .name = "i2s-if",
.id = -1,
.ctrlbit = S3C2443_SCLKCON_I2SCLK, .ctrlbit = S3C2443_SCLKCON_I2SCLK,
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
...@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = { ...@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "sdi", .name = "sdi",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SDI, .ctrlbit = S3C2443_PCLKCON_SDI,
}, { }, {
.name = "iis", .name = "iis",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIS, .ctrlbit = S3C2443_PCLKCON_IIS,
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c2410-spi.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI0, .ctrlbit = S3C2443_PCLKCON_SPI0,
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c2410-spi.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI1, .ctrlbit = S3C2443_PCLKCON_SPI1,
......
arch/arm/mach-s3c64xx/clock.c
浏览文件 @ 1e09939b
...@@ -39,7 +39,6 @@ ...@@ -39,7 +39,6 @@
static struct clk clk_ext_xtal_mux = { static struct clk clk_ext_xtal_mux = {
.name = "ext_xtal", .name = "ext_xtal",
.id = -1,
}; };
#define clk_fin_apll clk_ext_xtal_mux #define clk_fin_apll clk_ext_xtal_mux
...@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = { ...@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
struct clk clk_h2 = { struct clk clk_h2 = {
.name = "hclk2", .name = "hclk2",
.id = -1,
.rate = 0, .rate = 0,
}; };
struct clk clk_27m = { struct clk clk_27m = {
.name = "clk_27m", .name = "clk_27m",
.id = -1,
.rate = 27000000, .rate = 27000000,
}; };
...@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable) ...@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
struct clk clk_48m = { struct clk clk_48m = {
.name = "clk_48m", .name = "clk_48m",
.id = -1,
.rate = 48000000, .rate = 48000000,
.enable = clk_48m_ctrl, .enable = clk_48m_ctrl,
}; };
struct clk clk_xusbxti = { struct clk clk_xusbxti = {
.name = "xusbxti", .name = "xusbxti",
.id = -1,
.rate = 48000000, .rate = 48000000,
}; };
...@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable) ...@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "nand", .name = "nand",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC, .ctrlbit = S3C_CLKCON_PCLK_RTC,
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC, .ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC, .ctrlbit = S3C_CLKCON_PCLK_IIC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = 1, .devname = "s3c2440-i2c.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1, .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0, .ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, { }, {
.name = "iis", .name = "iis",
.id = 1, .devname = "samsung-i2s.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1, .ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, { }, {
#ifdef CONFIG_CPU_S3C6410 #ifdef CONFIG_CPU_S3C6410
.name = "iis", .name = "iis",
.id = -1, /* There's only one IISv4 port */
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_IIS2, .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
}, { }, {
#endif #endif
.name = "keypad", .name = "keypad",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD, .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0, .ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1, .ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, { }, {
.name = "spi_48m", .name = "spi_48m",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48, .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, { }, {
.name = "spi_48m", .name = "spi_48m",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48, .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, { }, {
.name = "48m", .name = "48m",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48, .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, { }, {
.name = "48m", .name = "48m",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48, .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, { }, {
.name = "48m", .name = "48m",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48, .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, { }, {
.name = "dma0", .name = "dma0",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA0, .ctrlbit = S3C_CLKCON_HCLK_DMA0,
}, { }, {
.name = "dma1", .name = "dma1",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA1, .ctrlbit = S3C_CLKCON_HCLK_DMA1,
...@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = { ...@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD, .ctrlbit = S3C_CLKCON_HCLK_LCD,
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO, .ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, { }, {
.name = "usb-host", .name = "usb-host",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST, .ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0, .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1, .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2, .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
}, { }, {
.name = "otg", .name = "otg",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_USB, .ctrlbit = S3C_CLKCON_HCLK_USB,
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM, .ctrlbit = S3C_CLKCON_PCLK_PWM,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c6400-uart.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0, .ctrlbit = S3C_CLKCON_PCLK_UART0,
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c6400-uart.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1, .ctrlbit = S3C_CLKCON_PCLK_UART1,
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c6400-uart.2",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2, .ctrlbit = S3C_CLKCON_PCLK_UART2,
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s3c6400-uart.3",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3, .ctrlbit = S3C_CLKCON_PCLK_UART3,
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT, .ctrlbit = S3C_CLKCON_PCLK_WDT,
}, { }, {
.name = "ac97", .name = "ac97",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97, .ctrlbit = S3C_CLKCON_PCLK_AC97,
}, { }, {
.name = "cfcon", .name = "cfcon",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_IHOST, .ctrlbit = S3C_CLKCON_HCLK_IHOST,
...@@ -334,7 +313,6 @@ static struct clk init_clocks[] = { ...@@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
static struct clk clk_fout_apll = { static struct clk clk_fout_apll = {
.name = "fout_apll", .name = "fout_apll",
.id = -1,
}; };
static struct clk *clk_src_apll_list[] = { static struct clk *clk_src_apll_list[] = {
...@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = { ...@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_apll = {
.clk = { .clk = {
.name = "mout_apll", .name = "mout_apll",
.id = -1,
}, },
.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
.sources = &clk_src_apll, .sources = &clk_src_apll,
...@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = { ...@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_epll = {
.clk = { .clk = {
.name = "mout_epll", .name = "mout_epll",
.id = -1,
}, },
.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
.sources = &clk_src_epll, .sources = &clk_src_epll,
...@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = { ...@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
static struct clksrc_clk clk_mout_mpll = { static struct clksrc_clk clk_mout_mpll = {
.clk = { .clk = {
.name = "mout_mpll", .name = "mout_mpll",
.id = -1,
}, },
.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
.sources = &clk_src_mpll, .sources = &clk_src_mpll,
...@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) ...@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
static struct clk clk_arm = { static struct clk clk_arm = {
.name = "armclk", .name = "armclk",
.id = -1,
.parent = &clk_mout_apll.clk, .parent = &clk_mout_apll.clk,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c64xx_clk_arm_get_rate, .get_rate = s3c64xx_clk_arm_get_rate,
...@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = { ...@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
static struct clk clk_dout_mpll = { static struct clk clk_dout_mpll = {
.name = "dout_mpll", .name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk, .parent = &clk_mout_mpll.clk,
.ops = &clk_dout_ops, .ops = &clk_dout_ops,
}; };
...@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = { ...@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
static struct clk clk_iis_cd0 = { static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0", .name = "iis_cdclk0",
.id = -1,
}; };
static struct clk clk_iis_cd1 = { static struct clk clk_iis_cd1 = {
.name = "iis_cdclk1", .name = "iis_cdclk1",
.id = -1,
}; };
static struct clk clk_iisv4_cd = { static struct clk clk_iisv4_cd = {
.name = "iis_cdclk_v4", .name = "iis_cdclk_v4",
.id = -1,
}; };
static struct clk clk_pcm_cd = { static struct clk clk_pcm_cd = {
.name = "pcm_cdclk", .name = "pcm_cdclk",
.id = -1,
}; };
static struct clk *clkset_audio0_list[] = { static struct clk *clkset_audio0_list[] = {
...@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "mmc_bus", .name = "mmc_bus",
.id = 0, .devname = "s3c-sdhci.0",
.ctrlbit = S3C_CLKCON_SCLK_MMC0, .ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "mmc_bus", .name = "mmc_bus",
.id = 1, .devname = "s3c-sdhci.1",
.ctrlbit = S3C_CLKCON_SCLK_MMC1, .ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "mmc_bus", .name = "mmc_bus",
.id = 2, .devname = "s3c-sdhci.2",
.ctrlbit = S3C_CLKCON_SCLK_MMC2, .ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "usb-bus-host", .name = "usb-bus-host",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UHOST, .ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UART, .ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
/* Where does UCLK0 come from? */ /* Where does UCLK0 come from? */
.clk = { .clk = {
.name = "spi-bus", .name = "spi-bus",
.id = 0, .devname = "s3c64xx-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0, .ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "spi-bus", .name = "spi-bus",
.id = 1, .devname = "s3c64xx-spi.1",
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
...@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "audio-bus", .name = "audio-bus",
.id = 0, .devname = "samsung-i2s.0",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0, .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "audio-bus", .name = "audio-bus",
.id = 1, .devname = "samsung-i2s.1",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1, .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "audio-bus", .name = "audio-bus",
.id = 2, .devname = "samsung-i2s.2",
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "irda-bus", .name = "irda-bus",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_IRDA, .ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
...@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "camera", .name = "camera",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_CAM, .ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
......
arch/arm/mach-s3c64xx/include/mach/clkdev.h 0 → 100644
浏览文件 @ 1e09939b
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif
arch/arm/mach-s3c64xx/include/mach/irqs.h
浏览文件 @ 1e09939b
...@@ -215,6 +215,7 @@ ...@@ -215,6 +215,7 @@
/* Compatibility */ /* Compatibility */
#define IRQ_ONENAND IRQ_ONENAND0 #define IRQ_ONENAND IRQ_ONENAND0
#define IRQ_I2S0 IRQ_S3C6410_IIS
#endif /* __ASM_MACH_S3C64XX_IRQS_H */ #endif /* __ASM_MACH_S3C64XX_IRQS_H */
arch/arm/mach-s3c64xx/include/mach/pm-core.h
浏览文件 @ 1e09939b
...@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void) ...@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
* the IRQ wake controls depending on the CPU we are running on */ * the IRQ wake controls depending on the CPU we are running on */
#define s3c_irqwake_eintallow ((1 << 28) - 1) #define s3c_irqwake_eintallow ((1 << 28) - 1)
#define s3c_irqwake_intallow (0) #define s3c_irqwake_intallow (~0)
static inline void s3c_pm_arch_update_uart(void __iomem *regs, static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save) struct pm_uart_save *save)
...@@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, ...@@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
save->ucon = new_ucon; save->ucon = new_ucon;
} }
} }
static inline void s3c_pm_restored_gpios(void)
{
/* ensure sleep mode has been cleared from the system */
__raw_writel(0, S3C64XX_SLPEN);
}
static inline void s3c_pm_saved_gpios(void)
{
/* turn on the sleep mode and keep it there, as it seems that during
* suspend the xCON registers get re-set and thus you can end up with
* problems between going to sleep and resuming.
*/
__raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
}
arch/arm/mach-s3c64xx/irq.c
浏览文件 @ 1e09939b
...@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = { ...@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = {
}, },
}; };
/* setup the sources the vic should advertise resume for, even though it
* is not doing the wake (set_irq_wake needs to be valid) */
#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{ {
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
/* initialise the pair of VICs */ /* initialise the pair of VICs */
vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
/* add the timer sub-irqs */ /* add the timer sub-irqs */
s3c_init_vic_timer_irq(5, IRQ_TIMER0); s3c_init_vic_timer_irq(5, IRQ_TIMER0);
......
arch/arm/mach-s5p64x0/Makefile
浏览文件 @ 1e09939b
...@@ -13,7 +13,7 @@ obj- := ...@@ -13,7 +13,7 @@ obj- :=
# Core support for S5P64X0 system # Core support for S5P64X0 system
obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
......
arch/arm/mach-s5p64x0/include/mach/clkdev.h 0 → 100644
浏览文件 @ 1e09939b
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif
arch/arm/mach-s5p64x0/include/mach/irqs.h
浏览文件 @ 1e09939b
...@@ -85,6 +85,8 @@ ...@@ -85,6 +85,8 @@
#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4 #define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5 #define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
#define IRQ_I2S0 IRQ_I2SV40
/* S5P6450 EINT feature will be added */ /* S5P6450 EINT feature will be added */
/* /*
......
arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
浏览文件 @ 1e09939b
...@@ -34,4 +34,14 @@ ...@@ -34,4 +34,14 @@
#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
/* External interrupt control registers for group0 */
#define EINT0CON0_OFFSET (0x900)
#define EINT0MASK_OFFSET (0x920)
#define EINT0PEND_OFFSET (0x924)
#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
#endif /* __ASM_ARCH_REGS_GPIO_H */ #endif /* __ASM_ARCH_REGS_GPIO_H */
arch/arm/mach-s5p64x0/irq-eint.c 0 → 100644
浏览文件 @ 1e09939b
/* arch/arm/mach-s5p64x0/irq-eint.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com/
*
* Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
*
* S5P64X0 - Interrupt handling for External Interrupts.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <plat/regs-irqtype.h>
#include <plat/gpio-cfg.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#define eint_offset(irq) ((irq) - IRQ_EINT(0))
static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = eint_offset(data->irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
if (offs > 15)
return -EINVAL;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -EINVAL;
}
shift = (offs / 2) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5P64X0_EINT0CON0);
/* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
else
s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
return 0;
}
/*
* s5p64x0_irq_demux_eint
*
* This function demuxes the IRQ from the group0 external interrupts,
* from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
* the specific handlers s5p64x0_irq_demux_eintX_Y.
*/
static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
{
u32 status = __raw_readl(S5P64X0_EINT0PEND);
u32 mask = __raw_readl(S5P64X0_EINT0MASK);
unsigned int irq;
status &= ~mask;
status >>= start;
status &= (1 << (end - start + 1)) - 1;
for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
if (status & 1)
generic_handle_irq(irq);
status >>= 1;
}
}
static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
s5p64x0_irq_demux_eint(0, 3);
}
static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
{
s5p64x0_irq_demux_eint(4, 11);
}
static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
struct irq_desc *desc)
{
s5p64x0_irq_demux_eint(12, 15);
}
static int s5p64x0_alloc_gc(void)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
S5P_VA_GPIO, handle_level_irq);
if (!gc) {
printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
"external interrupts failed\n", __func__);
return -EINVAL;
}
ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack;
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
ct->regs.ack = EINT0PEND_OFFSET;
ct->regs.mask = EINT0MASK_OFFSET;
irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
return 0;
}
static int __init s5p64x0_init_irq_eint(void)
{
int ret = s5p64x0_alloc_gc();
irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
return ret;
}
arch_initcall(s5p64x0_init_irq_eint);
arch/arm/mach-s5pc100/clock.c
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此差异已折叠。
arch/arm/mach-s5pc100/include/mach/clkdev.h 0 → 100644
浏览文件 @ 1e09939b
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif
arch/arm/mach-s5pv210/Kconfig
浏览文件 @ 1e09939b
...@@ -90,6 +90,7 @@ config MACH_GONI ...@@ -90,6 +90,7 @@ config MACH_GONI
select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC2
select S3C_DEV_I2C1 select S3C_DEV_I2C1
select S3C_DEV_I2C2 select S3C_DEV_I2C2
select S5P_DEV_MFC
select S3C_DEV_USB_HSOTG select S3C_DEV_USB_HSOTG
select S5P_DEV_ONENAND select S5P_DEV_ONENAND
select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_KEYPAD
......
arch/arm/mach-s5pv210/clock.c
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arch/arm/mach-s5pv210/cpu.c
浏览文件 @ 1e09939b
...@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void) ...@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void)
s5pv210_default_sdhci2(); s5pv210_default_sdhci2();
s5pv210_default_sdhci3(); s5pv210_default_sdhci3();
s3c_adc_setname("s3c64xx-adc"); s3c_adc_setname("samsung-adc-v3");
s3c_cfcon_setname("s5pv210-pata"); s3c_cfcon_setname("s5pv210-pata");
......
arch/arm/mach-s5pv210/dev-audio.c
浏览文件 @ 1e09939b
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
#include <mach/map.h> #include <mach/map.h>
#include <mach/dma.h> #include <mach/dma.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/regs-audss.h>
static const char *rclksrc[] = { static const char *rclksrc[] = {
[0] = "busclk", [0] = "busclk",
...@@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = { ...@@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR, | QUIRK_NEED_RSTCLR,
.src_clk = rclksrc, .src_clk = rclksrc,
.idma_addr = S5PV210_AUDSS_INT_MEM,
}, },
}, },
}; };
......
arch/arm/mach-s5pv210/include/mach/clkdev.h 0 → 100644
浏览文件 @ 1e09939b
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif
arch/arm/mach-s5pv210/include/mach/map.h
浏览文件 @ 1e09939b
...@@ -59,6 +59,8 @@ ...@@ -59,6 +59,8 @@
#define S5PV210_PA_CFCON 0xE8200000 #define S5PV210_PA_CFCON 0xE8200000
#define S5PV210_PA_MFC 0xF1700000
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_HSOTG 0xEC000000 #define S5PV210_PA_HSOTG 0xEC000000
...@@ -107,6 +109,7 @@ ...@@ -107,6 +109,7 @@
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1 #define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 #define S5P_PA_FIMC2 S5PV210_PA_FIMC2
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS #define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
#define S5P_PA_MFC S5PV210_PA_MFC
#define S5P_PA_ONENAND S5PC110_PA_ONENAND #define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA #define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV210_PA_SDRAM #define S5P_PA_SDRAM S5PV210_PA_SDRAM
......
arch/arm/mach-s5pv210/include/mach/pm-core.h
浏览文件 @ 1e09939b
...@@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, ...@@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
{ {
/* nothing here yet */ /* nothing here yet */
} }
static inline void s3c_pm_restored_gpios(void) { }
static inline void s3c_pm_saved_gpios(void) { }
arch/arm/mach-s5pv210/include/mach/regs-audss.h 0 → 100644
浏览文件 @ 1e09939b
/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
*
* Copyright (c) 2011 Samsung Electronics
* http://www.samsung.com
*
* S5PV210 Audio SubSystem clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_AUDSS_H
#define __PLAT_REGS_AUDSS_H __FILE__
#define S5PV210_AUDSS_INT_MEM (0xC0000000)
#endif /* _PLAT_REGS_AUDSS_H */
arch/arm/mach-s5pv210/mach-goni.c
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此差异已折叠。
arch/arm/mach-s5pv210/mach-smdkv210.c
浏览文件 @ 1e09939b
...@@ -267,6 +267,7 @@ static struct platform_device *smdkv210_devices[] __initdata = { ...@@ -267,6 +267,7 @@ static struct platform_device *smdkv210_devices[] __initdata = {
&s5pv210_device_iis0, &s5pv210_device_iis0,
&s5pv210_device_spdif, &s5pv210_device_spdif,
&samsung_asoc_dma, &samsung_asoc_dma,
&samsung_asoc_idma,
&samsung_device_keypad, &samsung_device_keypad,
&smdkv210_dm9000, &smdkv210_dm9000,
&smdkv210_lcd_lte480wv, &smdkv210_lcd_lte480wv,
......
arch/arm/plat-s3c24xx/clock-dclk.c
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arch/arm/plat-s3c24xx/include/mach/clkdev.h 0 → 100644
浏览文件 @ 1e09939b
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif
arch/arm/plat-s5p/Kconfig
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此差异已折叠。
arch/arm/plat-s5p/Makefile
浏览文件 @ 1e09939b
...@@ -25,11 +25,12 @@ obj-$(CONFIG_PM) += irq-pm.o ...@@ -25,11 +25,12 @@ obj-$(CONFIG_PM) += irq-pm.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o obj-$(CONFIG_S5P_HRT) += s5p-time.o
# devices # devices
obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o
obj-$(CONFIG_S5P_DEV_FIMD0) += dev-fimd0.o
obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o
obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o
......
arch/arm/plat-s5p/dev-fimd0.c 0 → 100644
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此差异已折叠。
arch/arm/plat-s5p/dev-mfc.c 0 → 100644
浏览文件 @ 1e09939b
此差异已折叠。
arch/arm/plat-s5p/include/plat/mfc.h 0 → 100644
浏览文件 @ 1e09939b
此差异已折叠。
arch/arm/plat-s5p/s5p-time.c
浏览文件 @ 1e09939b
此差异已折叠。
arch/arm/plat-samsung/adc.c
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此差异已折叠。
arch/arm/plat-samsung/clock.c
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此差异已折叠。
arch/arm/plat-samsung/dev-asocdma.c
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此差异已折叠。
arch/arm/plat-samsung/irq-uart.c
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此差异已折叠。
arch/arm/plat-samsung/pm.c
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此差异已折叠。
arch/arm/plat-samsung/pwm-clock.c
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此差异已折叠。
arch/arm/plat-samsung/time.c
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此差异已折叠。
drivers/tty/serial/s3c2410.c
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此差异已折叠。
drivers/tty/serial/s3c2412.c
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此差异已折叠。
drivers/tty/serial/s3c2440.c
浏览文件 @ 1e09939b
此差异已折叠。
drivers/tty/serial/s3c6400.c
浏览文件 @ 1e09939b
此差异已折叠。
drivers/tty/serial/s5pv210.c
浏览文件 @ 1e09939b
此差异已折叠。
drivers/tty/serial/samsung.c
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此差异已折叠。
drivers/tty/serial/samsung.h
浏览文件 @ 1e09939b
此差异已折叠。
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