drm/amd/display: do not reset lane count in EQ fallback

[Description]
According to DP1.4 specs we should not reset lane count back
when falling back in failing EQ training.
This causes PHY test pattern compliance to fail as infinite LT
when LT fails EQ to 4 RBR and fails CR in a loop.
Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -1302,8 +1302,6 @@ bool decide_fallback_link_setting(
 					current_link_setting->lane_count);
 		} else if (!reached_minimum_link_rate
 				(current_link_setting->link_rate)) {
-			current_link_setting->lane_count =
-				initial_link_settings.lane_count;
 			current_link_setting->link_rate =
 				reduce_link_rate(
 					current_link_setting->link_rate);