serial:ifx6x60:SPI header is decoded incorrectly

This patch is to correct the bit mapping of "MORE" and "CTS" in SPI frame header.
Per SPI protocol, SPI header is encoded with length of 4 byte, which is defined
as below:
bit 0 ~ 11: current data size;
bit 12: "MORE" bit;
bit 13: reserve
bit 14 ~ 15: reserve
bit 16 ~ 27: next data size
bit 28: RI
bit 29: DCD
bit 30: CTS/RTS
bit 31: DSR/DTR

According to above SPI header structure, the bit mapping of "MORE" and "CTS" is
incorrect in function ifx_spi_decode_spi_header();

Cc: Chen Jun <jun.d.chen@intel.com>
Signed-off-by: Nchanning <chao.bi@intel.com>
Acked-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/tty/serial/ifx6x60.c

@@ -64,8 +64,8 @@
 #include "ifx6x60.h"
 
 #define IFX_SPI_MORE_MASK		0x10
-#define IFX_SPI_MORE_BIT		12	/* bit position in u16 */
-#define IFX_SPI_CTS_BIT			13	/* bit position in u16 */
+#define IFX_SPI_MORE_BIT		4	/* bit position in u8 */
+#define IFX_SPI_CTS_BIT			6	/* bit position in u8 */
 #define IFX_SPI_MODE			SPI_MODE_1
 #define IFX_SPI_TTY_ID			0
 #define IFX_SPI_TIMEOUT_SEC		2