clk: pistachio: Add sanity checks on PLL configuration
When setting the PLL rates, check that: - VCO is within range - PFD is within range - PLL is disabled when postdiv is changed - postdiv2 <= postdiv1 Reviewed-by: NAndrew Bresticker <abrestic@chromium.org> Signed-off-by: NKevin Cernekee <cernekee@chromium.org> Signed-off-by: NEzequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Showing
想要评论请 注册 或 登录