提交 15777205 编写于 作者: P Paolo Ciarrocchi 提交者: Ingo Molnar

x86: coding style fixes to arch/x86/kernel/cpu/mcheck/p5.c

The patch make the file errors free.
Only 4 "WARNING: line over 80 characters" left.

arch/x86/kernel/cpu/mcheck/p5.o:
   text    data     bss     dec     hex filename
    452       0       4     456     1c8 p5.o.before
    452       0       4     456     1c8 p5.o.after
md5:
50c945ef150aa95bf0481cc3e1dc3315  p5.o.before.asm
50c945ef150aa95bf0481cc3e1dc3315  p5.o.after.asm
Signed-off-by: NPaolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>
上级 8cf36d2b
...@@ -9,20 +9,20 @@ ...@@ -9,20 +9,20 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/smp.h> #include <linux/smp.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/msr.h> #include <asm/msr.h>
#include "mce.h" #include "mce.h"
/* Machine check handler for Pentium class Intel */ /* Machine check handler for Pentium class Intel */
static void pentium_machine_check(struct pt_regs * regs, long error_code) static void pentium_machine_check(struct pt_regs *regs, long error_code)
{ {
u32 loaddr, hi, lotype; u32 loaddr, hi, lotype;
rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype); printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
if(lotype&(1<<5)) if (lotype&(1<<5))
printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id()); printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
add_taint(TAINT_MACHINE_CHECK); add_taint(TAINT_MACHINE_CHECK);
} }
...@@ -31,13 +31,13 @@ static void pentium_machine_check(struct pt_regs * regs, long error_code) ...@@ -31,13 +31,13 @@ static void pentium_machine_check(struct pt_regs * regs, long error_code)
void intel_p5_mcheck_init(struct cpuinfo_x86 *c) void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
{ {
u32 l, h; u32 l, h;
/*Check for MCE support */ /*Check for MCE support */
if( !cpu_has(c, X86_FEATURE_MCE) ) if (!cpu_has(c, X86_FEATURE_MCE))
return; return;
/* Default P5 to off as its often misconnected */ /* Default P5 to off as its often misconnected */
if(mce_disabled != -1) if (mce_disabled != -1)
return; return;
machine_check_vector = pentium_machine_check; machine_check_vector = pentium_machine_check;
wmb(); wmb();
...@@ -47,7 +47,7 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) ...@@ -47,7 +47,7 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
rdmsr(MSR_IA32_P5_MC_TYPE, l, h); rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
printk(KERN_INFO "Intel old style machine check architecture supported.\n"); printk(KERN_INFO "Intel old style machine check architecture supported.\n");
/* Enable MCE */ /* Enable MCE */
set_in_cr4(X86_CR4_MCE); set_in_cr4(X86_CR4_MCE);
printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id()); printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());
} }
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