提交 144ea15e 编写于 作者: J Josh Wu 提交者: Nicolas Ferre

ARM: at91/sama5: fix incorrect PMC pcr div definition

Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
上级 f6d35d67
...@@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base; ...@@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */
#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */
#define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */ #define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */
#define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */ #define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */
#define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */ #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
#endif #endif
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