提交 139cb65c 编写于 作者: D Dmytro Laktyushkin 提交者: Alex Deucher

drm/amd/display: make variable latency into a regkey option

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 cb26f892
......@@ -906,11 +906,16 @@ bool dcn_validate_bandwidth(
scaler_settings_calculation(v);
mode_support_and_system_configuration(v);
if (v->voltage_level == 0) {
if (v->voltage_level == 0 &&
(dc->public.debug.sr_exit_time_dpm0_ns
|| dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)) {
struct core_dc *dc_core = DC_TO_CORE(&dc->public);
v->sr_enter_plus_exit_time = 9.466f;
v->sr_exit_time = 7.849f;
if (dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)
v->sr_enter_plus_exit_time =
dc->public.debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
if (dc->public.debug.sr_exit_time_dpm0_ns)
v->sr_exit_time = dc->public.debug.sr_exit_time_dpm0_ns / 1000.0f;
dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time;
mode_support_and_system_configuration(v);
......
......@@ -171,6 +171,8 @@ struct dc_debug {
bool disable_pplib_wm_range;
bool use_dml_wm;
bool disable_pipe_split;
int sr_exit_time_dpm0_ns;
int sr_enter_plus_exit_time_dpm0_ns;
int sr_exit_time_ns;
int sr_enter_plus_exit_time_ns;
int urgent_latency_ns;
......
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