提交 0f0fbec9 编写于 作者: L Linus Torvalds

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:
 "A small set of fixes for the usual ARM/SOC irqchip drivers

   - A set of fixes for mbigen to handle multiple devices in a hardware
     module proper

   - A cleanup for the mbigen config option which was pointlessly user
     configurable.

   - A cleanup for tegra replacing open coded functionality by the
     proper core function

  The config cleanup touches arch/arm64/Kconfig.platforms to select the
  irq chip for the related platform"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/mbigen: Make CONFIG_HISILICON_IRQ_MBIGEN a hidden option
  ARM64: Kconfig: Select mbigen interrupt controller on Hisilicon platform
  irqchip/mbigen: Handle multiple device nodes in a mbigen module
  irqchip/mbigen: Adjust DT bindings to handle multiple devices in a module
  irqchip/tegra: Switch to use irq_domain_free_irqs_common
......@@ -21,6 +21,8 @@ Mbigen main node required properties:
- reg: Specifies the base physical address and size of the Mbigen
registers.
Mbigen sub node required properties:
------------------------------------------
- interrupt controller: Identifies the node as an interrupt controller
- msi-parent: Specifies the MSI controller this mbigen use.
......@@ -45,13 +47,23 @@ Mbigen main node required properties:
Examples:
mbigen_device_gmac:intc {
mbigen_chip_dsa {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xc0080000 0x0 0x10000>;
interrupt-controller;
msi-parent = <&its_dsa 0x40b1c>;
num-pins = <9>;
#interrupt-cells = <2>;
mbigen_gmac:intc_gmac {
interrupt-controller;
msi-parent = <&its_dsa 0x40b1c>;
num-pins = <9>;
#interrupt-cells = <2>;
};
mbigen_i2c:intc_i2c {
interrupt-controller;
msi-parent = <&its_dsa 0x40b0e>;
num-pins = <2>;
#interrupt-cells = <2>;
};
};
Devices connect to mbigen required properties:
......
......@@ -45,6 +45,7 @@ config ARCH_LAYERSCAPE
config ARCH_HISI
bool "Hisilicon SoC Family"
select HISILICON_IRQ_MBIGEN
help
This enables support for Hisilicon ARMv8 SoC family
......
......@@ -32,14 +32,6 @@ config ARM_GIC_V3_ITS
bool
select PCI_MSI_IRQ_DOMAIN
config HISILICON_IRQ_MBIGEN
bool "Support mbigen interrupt controller"
default n
depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
help
Enable the mbigen interrupt controller used on
Hisilicon platform.
config ARM_NVIC
bool
select IRQ_DOMAIN
......@@ -114,6 +106,12 @@ config DW_APB_ICTL
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
config HISILICON_IRQ_MBIGEN
bool
select ARM_GIC_V3
select ARM_GIC_V3_ITS
select GENERIC_MSI_IRQ_DOMAIN
config IMGPDC_IRQ
bool
select GENERIC_IRQ_CHIP
......
......@@ -239,8 +239,11 @@ static struct irq_domain_ops mbigen_domain_ops = {
static int mbigen_device_probe(struct platform_device *pdev)
{
struct mbigen_device *mgn_chip;
struct resource *res;
struct platform_device *child;
struct irq_domain *domain;
struct device_node *np;
struct device *parent;
struct resource *res;
u32 num_pins;
mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
......@@ -254,23 +257,30 @@ static int mbigen_device_probe(struct platform_device *pdev)
if (IS_ERR(mgn_chip->base))
return PTR_ERR(mgn_chip->base);
if (of_property_read_u32(pdev->dev.of_node, "num-pins", &num_pins) < 0) {
dev_err(&pdev->dev, "No num-pins property\n");
return -EINVAL;
}
for_each_child_of_node(pdev->dev.of_node, np) {
if (!of_property_read_bool(np, "interrupt-controller"))
continue;
domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
mbigen_write_msg,
&mbigen_domain_ops,
mgn_chip);
parent = platform_bus_type.dev_root;
child = of_platform_device_create(np, NULL, parent);
if (IS_ERR(child))
return PTR_ERR(child);
if (!domain)
return -ENOMEM;
if (of_property_read_u32(child->dev.of_node, "num-pins",
&num_pins) < 0) {
dev_err(&pdev->dev, "No num-pins property\n");
return -EINVAL;
}
domain = platform_msi_create_device_domain(&child->dev, num_pins,
mbigen_write_msg,
&mbigen_domain_ops,
mgn_chip);
if (!domain)
return -ENOMEM;
}
platform_set_drvdata(pdev, mgn_chip);
dev_info(&pdev->dev, "Allocated %d MSIs\n", num_pins);
return 0;
}
......
......@@ -275,22 +275,10 @@ static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
&parent_fwspec);
}
static void tegra_ictlr_domain_free(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs)
{
unsigned int i;
for (i = 0; i < nr_irqs; i++) {
struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
irq_domain_reset_irq_data(d);
}
}
static const struct irq_domain_ops tegra_ictlr_domain_ops = {
.translate = tegra_ictlr_domain_translate,
.alloc = tegra_ictlr_domain_alloc,
.free = tegra_ictlr_domain_free,
.free = irq_domain_free_irqs_common,
};
static int __init tegra_ictlr_init(struct device_node *node,
......
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