提交 0e5b4185 编写于 作者: J Julien Thierry 提交者: Caspar Zhang

arm/arm64: gic-v3: Add PMR and RPR accessors

task #25552995

commit e99da7c6f51b487280406d8dc31cc7532cfb2017 upstream

Add helper functions to access system registers related to interrupt
priorities: PMR and RPR.
Signed-off-by: NJulien Thierry <julien.thierry@arm.com>
Reviewed-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NZou Cao <zoucao@linux.alibaba.com>
Reviewed-by: Nluanshi <zhangliguang@linux.alibaba.com>
上级 c5cd3dff
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
#define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5) #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
#define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3) #define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3)
#define ICC_RPR __ACCESS_CP15(c12, 0, c11, 3)
#define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
#define ICC_AP0R0 __ICC_AP0Rx(0) #define ICC_AP0R0 __ICC_AP0Rx(0)
...@@ -245,6 +246,21 @@ static inline void gic_write_bpr1(u32 val) ...@@ -245,6 +246,21 @@ static inline void gic_write_bpr1(u32 val)
write_sysreg(val, ICC_BPR1); write_sysreg(val, ICC_BPR1);
} }
static inline u32 gic_read_pmr(void)
{
return read_sysreg(ICC_PMR);
}
static inline void gic_write_pmr(u32 val)
{
write_sysreg(val, ICC_PMR);
}
static inline u32 gic_read_rpr(void)
{
return read_sysreg(ICC_RPR);
}
/* /*
* Even in 32bit systems that use LPAE, there is no guarantee that the I/O * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
......
...@@ -114,6 +114,21 @@ static inline void gic_write_bpr1(u32 val) ...@@ -114,6 +114,21 @@ static inline void gic_write_bpr1(u32 val)
write_sysreg_s(val, SYS_ICC_BPR1_EL1); write_sysreg_s(val, SYS_ICC_BPR1_EL1);
} }
static inline u32 gic_read_pmr(void)
{
return read_sysreg_s(SYS_ICC_PMR_EL1);
}
static inline void gic_write_pmr(u32 val)
{
write_sysreg_s(val, SYS_ICC_PMR_EL1);
}
static inline u32 gic_read_rpr(void)
{
return read_sysreg_s(SYS_ICC_RPR_EL1);
}
#define gic_read_typer(c) readq_relaxed(c) #define gic_read_typer(c) readq_relaxed(c)
#define gic_write_irouter(v, c) writeq_relaxed(v, c) #define gic_write_irouter(v, c) writeq_relaxed(v, c)
#define gic_read_lpir(c) readq_relaxed(c) #define gic_read_lpir(c) readq_relaxed(c)
......
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