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提交 07c4dd34 编写于 作者: L Linus Torvalds
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Merge tag 'usb-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb 

Pull USB and PHY updates from Greg KH:
 "Here is the big USB pull request for 4.18-rc1.

  Lots of stuff here, the highlights are:

   - phy driver updates and new additions

   - usual set of xhci driver updates

   - normal set of musb updates

   - gadget driver updates and new controllers

   - typec work, it's getting closer to getting fully out of the staging
     portion of the tree.

   - lots of minor cleanups and bugfixes.

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'usb-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (263 commits)
  Revert "xhci: Reset Renesas uPD72020x USB controller for 32-bit DMA issue"
  xhci: Add quirk to zero 64bit registers on Renesas PCIe controllers
  xhci: Allow more than 32 quirks
  usb: xhci: force all memory allocations to node
  selftests: add test for USB over IP driver
  USB: typec: fsusb302: no need to check return value of debugfs_create_dir()
  USB: gadget: udc: s3c2410_udc: no need to check return value of debugfs_create functions
  USB: gadget: udc: renesas_usb3: no need to check return value of debugfs_create functions
  USB: gadget: udc: pxa27x_udc: no need to check return value of debugfs_create functions
  USB: gadget: udc: gr_udc: no need to check return value of debugfs_create functions
  USB: gadget: udc: bcm63xx_udc: no need to check return value of debugfs_create functions
  USB: udc: atmel_usba_udc: no need to check return value of debugfs_create functions
  USB: dwc3: no need to check return value of debugfs_create functions
  USB: dwc2: no need to check return value of debugfs_create functions
  USB: core: no need to check return value of debugfs_create functions
  USB: chipidea: no need to check return value of debugfs_create functions
  USB: ehci-hcd: no need to check return value of debugfs_create functions
  USB: fhci-hcd: no need to check return value of debugfs_create functions
  USB: fotg210-hcd: no need to check return value of debugfs_create functions
  USB: imx21-hcd: no need to check return value of debugfs_create functions
  ...
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Documentation/ABI/testing/sysfs-bus-usb
浏览文件 @ 07c4dd34
......@@ -189,6 +189,28 @@ Description:
The file will read "hotplug", "wired" and "not used" if the
information is available, and "unknown" otherwise.
What: /sys/bus/usb/devices/.../(hub interface)/portX/quirks
Date: May 2018
Contact: Nicolas Boichat <drinkcat@chromium.org>
Description:
In some cases, we care about time-to-active for devices
connected on a specific port (e.g. non-standard USB port like
pogo pins), where the device to be connected is known in
advance, and behaves well according to the specification.
This attribute is a bit-field that controls the behavior of
a specific port:
- Bit 0 of this field selects the "old" enumeration scheme,
as it is considerably faster (it only causes one USB reset
instead of 2).
The old enumeration scheme can also be selected globally
using /sys/module/usbcore/parameters/old_scheme_first, but
it is often not desirable as the new scheme was introduced to
increase compatibility with more devices.
- Bit 1 reduces TRSTRCY to the 10 ms that are required by the
USB 2.0 specification, instead of the 50 ms that are normally
used to help make enumeration work better on some high speed
devices.
What: /sys/bus/usb/devices/.../(hub interface)/portX/over_current_count
Date: February 2018
Contact: Richard Leitner <richard.leitner@skidata.com>
......@@ -236,3 +258,21 @@ Description:
Supported values are 0 - 15.
More information on how besl values map to microseconds can be found in
USB 2.0 ECN Errata for Link Power Management, section 4.10)
What: /sys/bus/usb/devices/.../rx_lanes
Date: March 2018
Contact: Mathias Nyman <mathias.nyman@linux.intel.com>
Description:
Number of rx lanes the device is using.
USB 3.2 adds Dual-lane support, 2 rx and 2 tx lanes over Type-C.
Inter-Chip SSIC devices support asymmetric lanes up to 4 lanes per
direction. Devices before USB 3.2 are single lane (rx_lanes = 1)
What: /sys/bus/usb/devices/.../tx_lanes
Date: March 2018
Contact: Mathias Nyman <mathias.nyman@linux.intel.com>
Description:
Number of tx lanes the device is using.
USB 3.2 adds Dual-lane support, 2 rx and 2 tx -lanes over Type-C.
Inter-Chip SSIC devices support asymmetric lanes up to 4 lanes per
direction. Devices before USB 3.2 are single lane (tx_lanes = 1)
Documentation/ABI/testing/sysfs-class-power
浏览文件 @ 07c4dd34
===== General Properties =====
What: /sys/class/power_supply/<supply_name>/manufacturer
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports the name of the device manufacturer.
Access: Read
Valid values: Represented as string
What: /sys/class/power_supply/<supply_name>/model_name
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports the name of the device model.
Access: Read
Valid values: Represented as string
What: /sys/class/power_supply/<supply_name>/serial_number
Date: January 2008
Contact: linux-pm@vger.kernel.org
Description:
Reports the serial number of the device.
Access: Read
Valid values: Represented as string
What: /sys/class/power_supply/<supply_name>/type
Date: May 2010
Contact: linux-pm@vger.kernel.org
Description:
Describes the main type of the supply.
Access: Read
Valid values: "Battery", "UPS", "Mains", "USB"
===== Battery Properties =====
What: /sys/class/power_supply/<supply_name>/capacity
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Fine grain representation of battery capacity.
Access: Read
Valid values: 0 - 100 (percent)
What: /sys/class/power_supply/<supply_name>/capacity_alert_max
Date: July 2012
Contact: linux-pm@vger.kernel.org
Description:
Maximum battery capacity trip-wire value where the supply will
notify user-space of the event. This is normally used for the
battery discharging scenario where user-space needs to know the
battery has dropped to an upper level so it can take
appropriate action (e.g. warning user that battery level is
low).
Access: Read, Write
Valid values: 0 - 100 (percent)
What: /sys/class/power_supply/<supply_name>/capacity_alert_min
Date: July 2012
Contact: linux-pm@vger.kernel.org
Description:
Minimum battery capacity trip-wire value where the supply will
notify user-space of the event. This is normally used for the
battery discharging scenario where user-space needs to know the
battery has dropped to a lower level so it can take
appropriate action (e.g. warning user that battery level is
critically low).
Access: Read, Write
Valid values: 0 - 100 (percent)
What: /sys/class/power_supply/<supply_name>/capacity_level
Date: June 2009
Contact: linux-pm@vger.kernel.org
Description:
Coarse representation of battery capacity.
Access: Read
Valid values: "Unknown", "Critical", "Low", "Normal", "High",
"Full"
What: /sys/class/power_supply/<supply_name>/current_avg
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports an average IBAT current reading for the battery, over a
fixed period. Normally devices will provide a fixed interval in
which they average readings to smooth out the reported value.
Access: Read
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/current_max
Date: October 2010
Contact: linux-pm@vger.kernel.org
Description:
Reports the maximum IBAT current allowed into the battery.
Access: Read
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/current_now
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports an instant, single IBAT current reading for the battery.
This value is not averaged/smoothed.
Access: Read
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/charge_type
Date: July 2009
Contact: linux-pm@vger.kernel.org
Description:
Represents the type of charging currently being applied to the
battery.
Access: Read
Valid values: "Unknown", "N/A", "Trickle", "Fast"
What: /sys/class/power_supply/<supply_name>/charge_term_current
Date: July 2014
Contact: linux-pm@vger.kernel.org
Description:
Reports the charging current value which is used to determine
when the battery is considered full and charging should end.
Access: Read
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/health
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports the health of the battery or battery side of charger
functionality.
Access: Read
Valid values: "Unknown", "Good", "Overheat", "Dead",
"Over voltage", "Unspecified failure", "Cold",
"Watchdog timer expire", "Safety timer expire"
What: /sys/class/power_supply/<supply_name>/precharge_current
Date: June 2017
Contact: linux-pm@vger.kernel.org
Description:
Reports the charging current applied during pre-charging phase
for a battery charge cycle.
Access: Read
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/present
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports whether a battery is present or not in the system.
Access: Read
Valid values:
0: Absent
1: Present
What: /sys/class/power_supply/<supply_name>/status
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Represents the charging status of the battery. Normally this
is read-only reporting although for some supplies this can be
used to enable/disable charging to the battery.
Access: Read, Write
Valid values: "Unknown", "Charging", "Discharging",
"Not charging", "Full"
What: /sys/class/power_supply/<supply_name>/technology
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Describes the battery technology supported by the supply.
Access: Read
Valid values: "Unknown", "NiMH", "Li-ion", "Li-poly", "LiFe",
"NiCd", "LiMn"
What: /sys/class/power_supply/<supply_name>/temp
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports the current TBAT battery temperature reading.
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/temp_alert_max
Date: July 2012
Contact: linux-pm@vger.kernel.org
Description:
Maximum TBAT temperature trip-wire value where the supply will
notify user-space of the event. This is normally used for the
battery charging scenario where user-space needs to know the
battery temperature has crossed an upper threshold so it can
take appropriate action (e.g. warning user that battery level is
critically high, and charging has stopped).
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/temp_alert_min
Date: July 2012
Contact: linux-pm@vger.kernel.org
Description:
Minimum TBAT temperature trip-wire value where the supply will
notify user-space of the event. This is normally used for the
battery charging scenario where user-space needs to know the
battery temperature has crossed a lower threshold so it can take
appropriate action (e.g. warning user that battery level is
high, and charging current has been reduced accordingly to
remedy the situation).
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/temp_max
Date: July 2014
Contact: linux-pm@vger.kernel.org
Description:
Reports the maximum allowed TBAT battery temperature for
charging.
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/temp_min
Date: July 2014
Contact: linux-pm@vger.kernel.org
Description:
Reports the minimum allowed TBAT battery temperature for
charging.
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/voltage_avg,
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports an average VBAT voltage reading for the battery, over a
fixed period. Normally devices will provide a fixed interval in
which they average readings to smooth out the reported value.
Access: Read
Valid values: Represented in microvolts
What: /sys/class/power_supply/<supply_name>/voltage_max,
Date: January 2008
Contact: linux-pm@vger.kernel.org
Description:
Reports the maximum safe VBAT voltage permitted for the battery,
during charging.
Access: Read
Valid values: Represented in microvolts
What: /sys/class/power_supply/<supply_name>/voltage_min,
Date: January 2008
Contact: linux-pm@vger.kernel.org
Description:
Reports the minimum safe VBAT voltage permitted for the battery,
during discharging.
Access: Read
Valid values: Represented in microvolts
What: /sys/class/power_supply/<supply_name>/voltage_now,
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports an instant, single VBAT voltage reading for the battery.
This value is not averaged/smoothed.
Access: Read
Valid values: Represented in microvolts
===== USB Properties =====
What: /sys/class/power_supply/<supply_name>/current_avg
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports an average IBUS current reading over a fixed period.
Normally devices will provide a fixed interval in which they
average readings to smooth out the reported value.
Access: Read
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/current_max
Date: October 2010
Contact: linux-pm@vger.kernel.org
Description:
Reports the maximum IBUS current the supply can support.
Access: Read
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/current_now
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports the IBUS current supplied now. This value is generally
read-only reporting, unless the 'online' state of the supply
is set to be programmable, in which case this value can be set
within the reported min/max range.
Access: Read, Write
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/input_current_limit
Date: July 2014
Contact: linux-pm@vger.kernel.org
Description:
Details the incoming IBUS current limit currently set in the
supply. Normally this is configured based on the type of
connection made (e.g. A configured SDP should output a maximum
of 500mA so the input current limit is set to the same value).
Access: Read, Write
Valid values: Represented in microamps
What: /sys/class/power_supply/<supply_name>/online,
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Indicates if VBUS is present for the supply. When the supply is
online, and the supply allows it, then it's possible to switch
between online states (e.g. Fixed -> Programmable for a PD_PPS
USB supply so voltage and current can be controlled).
Access: Read, Write
Valid values:
0: Offline
1: Online Fixed - Fixed Voltage Supply
2: Online Programmable - Programmable Voltage Supply
What: /sys/class/power_supply/<supply_name>/temp
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports the current supply temperature reading. This would
normally be the internal temperature of the device itself (e.g
TJUNC temperature of an IC)
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/temp_alert_max
Date: July 2012
Contact: linux-pm@vger.kernel.org
Description:
Maximum supply temperature trip-wire value where the supply will
notify user-space of the event. This is normally used for the
charging scenario where user-space needs to know the supply
temperature has crossed an upper threshold so it can take
appropriate action (e.g. warning user that the supply
temperature is critically high, and charging has stopped to
remedy the situation).
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/temp_alert_min
Date: July 2012
Contact: linux-pm@vger.kernel.org
Description:
Minimum supply temperature trip-wire value where the supply will
notify user-space of the event. This is normally used for the
charging scenario where user-space needs to know the supply
temperature has crossed a lower threshold so it can take
appropriate action (e.g. warning user that the supply
temperature is high, and charging current has been reduced
accordingly to remedy the situation).
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/temp_max
Date: July 2014
Contact: linux-pm@vger.kernel.org
Description:
Reports the maximum allowed supply temperature for operation.
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/temp_min
Date: July 2014
Contact: linux-pm@vger.kernel.org
Description:
Reports the mainimum allowed supply temperature for operation.
Access: Read
Valid values: Represented in 1/10 Degrees Celsius
What: /sys/class/power_supply/<supply_name>/usb_type
Date: March 2018
Contact: linux-pm@vger.kernel.org
Description:
Reports what type of USB connection is currently active for
the supply, for example it can show if USB-PD capable source
is attached.
Access: Read-Only
Valid values: "Unknown", "SDP", "DCP", "CDP", "ACA", "C", "PD",
"PD_DRP", "PD_PPS", "BrickID"
What: /sys/class/power_supply/<supply_name>/voltage_max
Date: January 2008
Contact: linux-pm@vger.kernel.org
Description:
Reports the maximum VBUS voltage the supply can support.
Access: Read
Valid values: Represented in microvolts
What: /sys/class/power_supply/<supply_name>/voltage_min
Date: January 2008
Contact: linux-pm@vger.kernel.org
Description:
Reports the minimum VBUS voltage the supply can support.
Access: Read
Valid values: Represented in microvolts
What: /sys/class/power_supply/<supply_name>/voltage_now
Date: May 2007
Contact: linux-pm@vger.kernel.org
Description:
Reports the VBUS voltage supplied now. This value is generally
read-only reporting, unless the 'online' state of the supply
is set to be programmable, in which case this value can be set
within the reported min/max range.
Access: Read, Write
Valid values: Represented in microvolts
===== Device Specific Properties =====
What: /sys/class/power/ds2760-battery.*/charge_now
Date: May 2010
KernelVersion: 2.6.35
......
Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt 0 → 100644
浏览文件 @ 07c4dd34
MediaTek XS-PHY binding
--------------------------
The XS-PHY controller supports physical layer functionality for USB3.1
GEN2 controller on MediaTek SoCs.
Required properties (controller (parent) node):
- compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
soc-model is the name of SoC, such as mt3611 etc;
when using "mediatek,xsphy" compatible string, you need SoC specific
ones in addition, one of:
- "mediatek,mt3611-xsphy"
- #address-cells, #size-cells : should use the same values as the root node
- ranges: must be present
Optional properties (controller (parent) node):
- reg : offset and length of register shared by multiple U3 ports,
exclude port's private register, if only U2 ports provided,
shouldn't use the property.
- mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
calibrate
- mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
SoC process
Required nodes : a sub-node is required for each port the controller
provides. Address range information including the usual
'reg' property is used inside these nodes to describe
the controller's topology.
Required properties (port (child) node):
- reg : address and length of the register set for the port.
- clocks : a list of phandle + clock-specifier pairs, one for each
entry in clock-names
- clock-names : must contain
"ref": 48M reference clock for HighSpeed analog phy; and 26M
reference clock for SuperSpeedPlus analog phy, sometimes is
24M, 25M or 27M, depended on platform.
- #phy-cells : should be 1
cell after port phandle is phy type from:
- PHY_TYPE_USB2
- PHY_TYPE_USB3
The following optional properties are only for debug or HQA test
Optional properties (PHY_TYPE_USB2 port (child) node):
- mediatek,eye-src : u32, the value of slew rate calibrate
- mediatek,eye-vrt : u32, the selection of VRT reference voltage
- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
- mediatek,efuse-intr : u32, the selection of Internal Resistor
Optional properties (PHY_TYPE_USB3 port (child) node):
- mediatek,efuse-intr : u32, the selection of Internal Resistor
- mediatek,efuse-tx-imp : u32, the selection of TX Impedance
- mediatek,efuse-rx-imp : u32, the selection of RX Impedance
Banks layout of xsphy
-------------------------------------------------------------
port offset bank
u2 port0 0x0000 MISC
0x0100 FMREG
0x0300 U2PHY_COM
u2 port1 0x1000 MISC
0x1100 FMREG
0x1300 U2PHY_COM
u2 port2 0x2000 MISC
...
u31 common 0x3000 DIG_GLB
0x3100 PHYA_GLB
u31 port0 0x3400 DIG_LN_TOP
0x3500 DIG_LN_TX0
0x3600 DIG_LN_RX0
0x3700 DIG_LN_DAIF
0x3800 PHYA_LN
u31 port1 0x3a00 DIG_LN_TOP
0x3b00 DIG_LN_TX0
0x3c00 DIG_LN_RX0
0x3d00 DIG_LN_DAIF
0x3e00 PHYA_LN
...
DIG_GLB & PHYA_GLB are shared by U31 ports.
Example:
u3phy: usb-phy@11c40000 {
compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
reg = <0 0x11c43000 0 0x0200>;
mediatek,src-ref-clk-mhz = <26>;
mediatek,src-coef = <17>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
u2port0: usb-phy@11c40000 {
reg = <0 0x11c40000 0 0x0400>;
clocks = <&clk48m>;
clock-names = "ref";
mediatek,eye-src = <4>;
#phy-cells = <1>;
};
u3port0: usb-phy@11c43000 {
reg = <0 0x11c43400 0 0x0500>;
clocks = <&clk26m>;
clock-names = "ref";
mediatek,efuse-intr = <28>;
#phy-cells = <1>;
};
};
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
浏览文件 @ 07c4dd34
......@@ -9,7 +9,8 @@ Required properties:
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
"qcom,qmp-v3-usb3-phy" for USB3 QMP V3 phy.
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
- reg: offset and length of register set for PHY's common serdes block.
......
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
浏览文件 @ 07c4dd34
......@@ -6,7 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
Required properties:
- compatible: compatible list, contains
"qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
"qcom,qusb2-v2-phy" for QUSB2 V2 PHY.
"qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
- reg: offset and length of the PHY register set.
- #phy-cells: must be 0.
......@@ -27,6 +27,27 @@ Optional properties:
tuning parameter value for qusb2 phy.
- qcom,tcsr-syscon: Phandle to TCSR syscon register region.
- qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be
added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
tuning parameter that may vary for different boards of same SOC.
This property is applicable to only QUSB2 v2 PHY (sdm845).
- qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX
output current.
Possible range is - 15mA to 24mA (stepsize of 600 uA).
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
This property is applicable to only QUSB2 v2 PHY (sdm845).
Default value is 22.2mA for sdm845.
- qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level.
Possible range is 0 to 15% (stepsize of 5%).
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
This property is applicable to only QUSB2 v2 PHY (sdm845).
Default value is 10% for sdm845.
- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX
pre-emphasis (specified using qcom,preemphasis-level) must be in
effect. Duration could be half-bit of full-bit.
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
This property is applicable to only QUSB2 v2 PHY (sdm845).
Default value is full-bit width for sdm845.
Example:
hsusb_phy: phy@7411000 {
......
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
浏览文件 @ 07c4dd34
......@@ -76,6 +76,10 @@ Optional properties:
needs to make sure it does not send more than 90%
maximum_periodic_data_per_frame. The use case is multiple transactions, but
less frame rate.
- mux-controls: The mux control for toggling host/device output of this
controller. It's expected that a mux state of 0 indicates device mode and a
mux state of 1 indicates host mode.
- mux-control-names: Shall be "usb_switch" if mux-controls is specified.
i.mx specific properties
- fsl,usbmisc: phandler of non-core register device, with one
......@@ -102,4 +106,6 @@ Example:
rx-burst-size-dword = <0x10>;
extcon = <0>, <&usb_id>;
phy-clkgate-delay-us = <400>;
mux-controls = <&usb_switch>;
mux-control-names = "usb_switch";
};
Documentation/devicetree/bindings/usb/dwc3.txt
浏览文件 @ 07c4dd34
......@@ -7,6 +7,26 @@ Required properties:
- compatible: must be "snps,dwc3"
- reg : Address and length of the register set for the device
- interrupts: Interrupts used by the dwc3 controller.
- clock-names: should contain "ref", "bus_early", "suspend"
- clocks: list of phandle and clock specifier pairs corresponding to
entries in the clock-names property.
Exception for clocks:
clocks are optional if the parent node (i.e. glue-layer) is compatible to
one of the following:
"amlogic,meson-axg-dwc3"
"amlogic,meson-gxl-dwc3"
"cavium,octeon-7130-usb-uctl"
"qcom,dwc3"
"samsung,exynos5250-dwusb3"
"samsung,exynos7-dwusb3"
"sprd,sc9860-dwc3"
"st,stih407-dwc3"
"ti,am437x-dwc3"
"ti,dwc3"
"ti,keystone-dwc3"
"rockchip,rk3399-dwc3"
"xlnx,zynqmp-dwc3"
Optional properties:
- usb-phy : array of phandle for the PHY device. The first element
......@@ -15,6 +35,7 @@ Optional properties:
- phys: from the *Generic PHY* bindings
- phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
or "usb3-phy".
- resets: a single pair of phandle and reset specifier
- snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
- snps,disable_scramble_quirk: true when SW should disable data scrambling.
Only really useful for FPGA builds.
......
Documentation/devicetree/bindings/usb/fcs,fusb302.txt
浏览文件 @ 07c4dd34
......@@ -6,12 +6,6 @@ Required properties :
- interrupts : Interrupt specifier
Optional properties :
- fcs,max-sink-microvolt : Maximum voltage to negotiate when configured as sink
- fcs,max-sink-microamp : Maximum current to negotiate when configured as sink
- fcs,max-sink-microwatt : Maximum power to negotiate when configured as sink
If this is less then max-sink-microvolt *
max-sink-microamp then the configured current will
be clamped.
- fcs,operating-sink-microwatt :
Minimum amount of power accepted from a sink
when negotiating
......
Documentation/devicetree/bindings/usb/hisilicon,histb-xhci.txt 0 → 100644
浏览文件 @ 07c4dd34
HiSilicon STB xHCI
The device node for HiSilicon STB xHCI host controller
Required properties:
- compatible: should be "hisilicon,hi3798cv200-xhci"
- reg: specifies physical base address and size of the registers
- interrupts : interrupt used by the controller
- clocks: a list of phandle + clock-specifier pairs, one for each
entry in clock-names
- clock-names: must contain
"bus": for bus clock
"utmi": for utmi clock
"pipe": for pipe clock
"suspend": for suspend clock
- resets: a list of phandle and reset specifier pairs as listed in
reset-names property.
- reset-names: must contain
"soft": for soft reset
- phys: a list of phandle + phy specifier pairs
- phy-names: must contain at least one of following:
"inno": for inno phy
"combo": for combo phy
Optional properties:
- usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
- usb3-lpm-capable: determines if platform is USB3 LPM capable
- imod-interval-ns: default interrupt moderation interval is 40000ns
Example:
xhci0: xchi@f98a0000 {
compatible = "hisilicon,hi3798cv200-xhci";
reg = <0xf98a0000 0x10000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_USB3_BUS_CLK>,
<&crg HISTB_USB3_UTMI_CLK>,
<&crg HISTB_USB3_PIPE_CLK>,
<&crg HISTB_USB3_SUSPEND_CLK>;
clock-names = "bus", "utmi", "pipe", "suspend";
resets = <&crg 0xb0 12>;
reset-names = "soft";
phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>;
phy-names = "inno", "combo";
};
Documentation/devicetree/bindings/usb/qcom,dwc3.txt
浏览文件 @ 07c4dd34
Qualcomm SuperSpeed DWC3 USB SoC controller
Required properties:
- compatible: should contain "qcom,dwc3"
- compatible: Compatible list, contains
"qcom,dwc3"
"qcom,msm8996-dwc3" for msm8996 SOC.
"qcom,sdm845-dwc3" for sdm845 SOC.
- reg: Offset and length of register set for QSCRATCH wrapper
- power-domains: specifies a phandle to PM domain provider node
- clocks: A list of phandle + clock-specifier pairs for the
clocks listed in clock-names
- clock-names: Should contain the following:
- clock-names: Should contain the following:
"core" Master/Core clock, have to be >= 125 MHz for SS
operation and >= 60MHz for HS operation
"mock_utmi" Mock utmi clock needed for ITP/SOF generation in
host mode. Its frequency should be 19.2MHz.
"sleep" Sleep clock, used for wakeup when USB3 core goes
into low power mode (U3).
Optional clocks:
"iface" System bus AXI clock. Not present on all platforms
"sleep" Sleep clock, used when USB3 core goes into low
power mode (U3).
"iface" System bus AXI clock.
Not present on "qcom,msm8996-dwc3" compatible.
"cfg_noc" System Config NOC clock.
Not present on "qcom,msm8996-dwc3" compatible.
- assigned-clocks: Should be:
MOCK_UTMI_CLK
MASTER_CLK
- assigned-clock-rates: Should be:
19.2Mhz (192000000) for MOCK_UTMI_CLK
>=125Mhz (125000000) for MASTER_CLK in SS mode
>=60Mhz (60000000) for MASTER_CLK in HS mode
Optional properties:
- resets: Phandle to reset control that resets core and wrapper.
- interrupts: specifies interrupts from controller wrapper used
to wakeup from low power/susepnd state. Must contain
one or more entry for interrupt-names property
- interrupt-names: Must include the following entries:
- "hs_phy_irq": The interrupt that is asserted when a
wakeup event is received on USB2 bus
- "ss_phy_irq": The interrupt that is asserted when a
wakeup event is received on USB3 bus
- "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate
interrupts for any wakeup event on DM and DP lines
- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement.
Used when dwc3 operates without SSPHY and only
HS/FS/LS modes are supported.
Required child node:
A child node must exist to represent the core DWC3 IP block. The name of
the node is not important. The content of the node is defined in dwc3.txt.
Phy documentation is provided in the following places:
Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY
Example device nodes:
hs_phy: phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>;
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
compatible = "qcom,qusb2-v2-phy";
...
};
ss_phy: phy@100f8830 {
compatible = "qcom,dwc3-ss-usb-phy";
reg = <0x100f8830 0x30>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
compatible = "qcom,qmp-v3-usb3-phy";
...
};
usb3_0: usb30@0 {
usb3_0: usb30@a6f8800 {
compatible = "qcom,dwc3";
reg = <0xa6f8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core";
ranges;
interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "core", "mock_utmi", "sleep";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <133000000>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
power-domains = <&gcc USB30_PRIM_GDSC>;
qcom,select-utmi-as-pipe-clk;
dwc3@10000000 {
compatible = "snps,dwc3";
......
Documentation/devicetree/bindings/usb/richtek,rt1711h.txt 0 → 100644
浏览文件 @ 07c4dd34
Richtek RT1711H TypeC PD Controller.
Required properties:
- compatible : Must be "richtek,rt1711h".
- reg : Must be 0x4e, it's slave address of RT1711H.
- interrupt-parent : the phandle for the interrupt controller that
provides interrupts for this device.
- interrupts : <a b> where a is the interrupt number and b represents an
encoding of the sense and level information for the interrupt.
Example :
rt1711h@4e {
compatible = "richtek,rt1711h";
reg = <0x4e>;
interrupt-parent = <&gpio26>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
Documentation/driver-api/usb/dwc3.rst
浏览文件 @ 07c4dd34
......@@ -674,9 +674,8 @@ operations, both of which can be traced. Format is::
__entry->flags & DWC3_EP_ENABLED ? 'E' : 'e',
__entry->flags & DWC3_EP_STALL ? 'S' : 's',
__entry->flags & DWC3_EP_WEDGE ? 'W' : 'w',
__entry->flags & DWC3_EP_BUSY ? 'B' : 'b',
__entry->flags & DWC3_EP_TRANSFER_STARTED ? 'B' : 'b',
__entry->flags & DWC3_EP_PENDING_REQUEST ? 'P' : 'p',
__entry->flags & DWC3_EP_MISSED_ISOC ? 'M' : 'm',
__entry->flags & DWC3_EP_END_TRANSFER_PENDING ? 'E' : 'e',
__entry->direction ? '<' : '>'
)
......
MAINTAINERS
浏览文件 @ 07c4dd34
......@@ -2331,6 +2331,14 @@ S: Maintained
F: drivers/gpio/gpio-ath79.c
F: Documentation/devicetree/bindings/gpio/gpio-ath79.txt
ATHEROS 71XX/9XXX USB PHY DRIVER
M: Alban Bedel <albeu@free.fr>
W: https://github.com/AlbanBedel/linux
T: git git://github.com/AlbanBedel/linux
S: Maintained
F: drivers/phy/qualcomm/phy-ath79-usb.c
F: Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
ATHEROS ATH GENERIC UTILITIES
M: Kalle Valo <kvalo@codeaurora.org>
L: linux-wireless@vger.kernel.org
......@@ -11267,6 +11275,7 @@ M: Sebastian Reichel <sre@kernel.org>
L: linux-pm@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git
S: Maintained
F: Documentation/ABI/testing/sysfs-class-power
F: Documentation/devicetree/bindings/power/supply/
F: include/linux/power_supply.h
F: drivers/power/supply/
......@@ -14692,6 +14701,7 @@ S: Maintained
F: Documentation/usb/usbip_protocol.txt
F: drivers/usb/usbip/
F: tools/usb/usbip/
F: tools/testing/selftests/drivers/usb/usbip/
USB PEGASUS DRIVER
M: Petko Manolov <petkan@nucleusys.com>
......
drivers/i2c/busses/Kconfig
浏览文件 @ 07c4dd34
......@@ -202,8 +202,7 @@ config I2C_CHT_WC
Note this controller is hooked up to a TI bq24292i charger-IC,
combined with a FUSB302 Type-C port-controller as such it is advised
to also select CONFIG_CHARGER_BQ24190=m and CONFIG_TYPEC_FUSB302=m
(the fusb302 driver currently is in drivers/staging).
to also select CONFIG_TYPEC_FUSB302=m.
config I2C_NFORCE2
tristate "Nvidia nForce2, nForce3 and nForce4"
......
drivers/nfc/pn533/usb.c
浏览文件 @ 07c4dd34
......@@ -62,6 +62,9 @@ struct pn533_usb_phy {
struct urb *out_urb;
struct urb *in_urb;
struct urb *ack_urb;
u8 *ack_buffer;
struct pn533 *priv;
};
......@@ -150,13 +153,16 @@ static int pn533_usb_send_ack(struct pn533 *dev, gfp_t flags)
struct pn533_usb_phy *phy = dev->phy;
static const u8 ack[6] = {0x00, 0x00, 0xff, 0x00, 0xff, 0x00};
/* spec 7.1.1.3: Preamble, SoPC (2), ACK Code (2), Postamble */
int rc;
phy->out_urb->transfer_buffer = (u8 *)ack;
phy->out_urb->transfer_buffer_length = sizeof(ack);
rc = usb_submit_urb(phy->out_urb, flags);
if (!phy->ack_buffer) {
phy->ack_buffer = kmemdup(ack, sizeof(ack), flags);
if (!phy->ack_buffer)
return -ENOMEM;
}
return rc;
phy->ack_urb->transfer_buffer = phy->ack_buffer;
phy->ack_urb->transfer_buffer_length = sizeof(ack);
return usb_submit_urb(phy->ack_urb, flags);
}
static int pn533_usb_send_frame(struct pn533 *dev,
......@@ -375,26 +381,31 @@ static int pn533_acr122_poweron_rdr(struct pn533_usb_phy *phy)
/* Power on th reader (CCID cmd) */
u8 cmd[10] = {PN533_ACR122_PC_TO_RDR_ICCPOWERON,
0, 0, 0, 0, 0, 0, 3, 0, 0};
char *buffer;
int transferred;
int rc;
void *cntx;
struct pn533_acr122_poweron_rdr_arg arg;
dev_dbg(&phy->udev->dev, "%s\n", __func__);
buffer = kmemdup(cmd, sizeof(cmd), GFP_KERNEL);
if (!buffer)
return -ENOMEM;
init_completion(&arg.done);
cntx = phy->in_urb->context; /* backup context */
phy->in_urb->complete = pn533_acr122_poweron_rdr_resp;
phy->in_urb->context = &arg;
phy->out_urb->transfer_buffer = cmd;
phy->out_urb->transfer_buffer_length = sizeof(cmd);
print_hex_dump_debug("ACR122 TX: ", DUMP_PREFIX_NONE, 16, 1,
cmd, sizeof(cmd), false);
rc = usb_submit_urb(phy->out_urb, GFP_KERNEL);
if (rc) {
rc = usb_bulk_msg(phy->udev, phy->out_urb->pipe, buffer, sizeof(cmd),
&transferred, 0);
kfree(buffer);
if (rc || (transferred != sizeof(cmd))) {
nfc_err(&phy->udev->dev,
"Reader power on cmd error %d\n", rc);
return rc;
......@@ -490,8 +501,9 @@ static int pn533_usb_probe(struct usb_interface *interface,
phy->in_urb = usb_alloc_urb(0, GFP_KERNEL);
phy->out_urb = usb_alloc_urb(0, GFP_KERNEL);
phy->ack_urb = usb_alloc_urb(0, GFP_KERNEL);
if (!phy->in_urb || !phy->out_urb)
if (!phy->in_urb || !phy->out_urb || !phy->ack_urb)
goto error;
usb_fill_bulk_urb(phy->in_urb, phy->udev,
......@@ -501,7 +513,9 @@ static int pn533_usb_probe(struct usb_interface *interface,
usb_fill_bulk_urb(phy->out_urb, phy->udev,
usb_sndbulkpipe(phy->udev, out_endpoint),
NULL, 0, pn533_send_complete, phy);
usb_fill_bulk_urb(phy->ack_urb, phy->udev,
usb_sndbulkpipe(phy->udev, out_endpoint),
NULL, 0, pn533_send_complete, phy);
switch (id->driver_info) {
case PN533_DEVICE_STD:
......@@ -554,6 +568,7 @@ static int pn533_usb_probe(struct usb_interface *interface,
error:
usb_free_urb(phy->in_urb);
usb_free_urb(phy->out_urb);
usb_free_urb(phy->ack_urb);
usb_put_dev(phy->udev);
kfree(in_buf);
......@@ -573,10 +588,13 @@ static void pn533_usb_disconnect(struct usb_interface *interface)
usb_kill_urb(phy->in_urb);
usb_kill_urb(phy->out_urb);
usb_kill_urb(phy->ack_urb);
kfree(phy->in_urb->transfer_buffer);
usb_free_urb(phy->in_urb);
usb_free_urb(phy->out_urb);
usb_free_urb(phy->ack_urb);
kfree(phy->ack_buffer);
nfc_info(&interface->dev, "NXP PN533 NFC device disconnected\n");
}
......
drivers/phy/mediatek/Kconfig
浏览文件 @ 07c4dd34
......@@ -12,3 +12,12 @@ config PHY_MTK_TPHY
different banks layout, the T-PHY with shared banks between
multi-ports is first version, otherwise is second veriosn,
so you can easily distinguish them by banks layout.
config PHY_MTK_XSPHY
tristate "MediaTek XS-PHY Driver"
depends on ARCH_MEDIATEK && OF
select GENERIC_PHY
help
Enable this to support the SuperSpeedPlus XS-PHY transceiver for
USB3.1 GEN2 controllers on MediaTek chips. The driver supports
multiple USB2.0, USB3.1 GEN2 ports.
drivers/phy/mediatek/Makefile
浏览文件 @ 07c4dd34
......@@ -3,3 +3,4 @@
#
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
drivers/phy/mediatek/phy-mtk-xsphy.c 0 → 100644
浏览文件 @ 07c4dd34
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek USB3.1 gen2 xsphy Driver
*
* Copyright (c) 2018 MediaTek Inc.
* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
*
*/
#include <dt-bindings/phy/phy.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
/* u2 phy banks */
#define SSUSB_SIFSLV_MISC 0x000
#define SSUSB_SIFSLV_U2FREQ 0x100
#define SSUSB_SIFSLV_U2PHY_COM 0x300
/* u3 phy shared banks */
#define SSPXTP_SIFSLV_DIG_GLB 0x000
#define SSPXTP_SIFSLV_PHYA_GLB 0x100
/* u3 phy banks */
#define SSPXTP_SIFSLV_DIG_LN_TOP 0x000
#define SSPXTP_SIFSLV_DIG_LN_TX0 0x100
#define SSPXTP_SIFSLV_DIG_LN_RX0 0x200
#define SSPXTP_SIFSLV_DIG_LN_DAIF 0x300
#define SSPXTP_SIFSLV_PHYA_LN 0x400
#define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00)
#define P2F_RG_FREQDET_EN BIT(24)
#define P2F_RG_CYCLECNT GENMASK(23, 0)
#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
#define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c)
#define XSP_U2FREQ_FMMONR1 ((SSUSB_SIFSLV_U2FREQ) + 0x10)
#define P2F_RG_FRCK_EN BIT(8)
#define P2F_USB_FM_VALID BIT(0)
#define XSP_USBPHYACR0 ((SSUSB_SIFSLV_U2PHY_COM) + 0x00)
#define P2A0_RG_INTR_EN BIT(5)
#define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04)
#define P2A1_RG_INTR_CAL GENMASK(23, 19)
#define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
#define P2A1_RG_VRT_SEL GENMASK(14, 12)
#define P2A1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
#define P2A1_RG_TERM_SEL GENMASK(10, 8)
#define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
#define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014)
#define P2A5_RG_HSTX_SRCAL_EN BIT(15)
#define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)
#define P2A5_RG_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
#define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
#define P2A6_RG_BC11_SW_EN BIT(23)
#define P2A6_RG_OTG_VBUSCMP_EN BIT(20)
#define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C)
#define P2D_FORCE_IDDIG BIT(9)
#define P2D_RG_VBUSVALID BIT(5)
#define P2D_RG_SESSEND BIT(4)
#define P2D_RG_AVALID BIT(2)
#define P2D_RG_IDDIG BIT(1)
#define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00)
#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16)
#define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x) ((0x3f & (x)) << 16)
#define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04)
#define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0)
#define RG_XTP_LN0_TX_IMPSEL_VAL(x) (0x1f & (x))
#define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014)
#define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0)
#define RG_XTP_LN0_RX_IMPSEL_VAL(x) (0x1f & (x))
#define XSP_REF_CLK 26 /* MHZ */
#define XSP_SLEW_RATE_COEF 17
#define XSP_SR_COEF_DIVISOR 1000
#define XSP_FM_DET_CYCLE_CNT 1024
struct xsphy_instance {
struct phy *phy;
void __iomem *port_base;
struct clk *ref_clk; /* reference clock of anolog phy */
u32 index;
u32 type;
/* only for HQA test */
int efuse_intr;
int efuse_tx_imp;
int efuse_rx_imp;
/* u2 eye diagram */
int eye_src;
int eye_vrt;
int eye_term;
};
struct mtk_xsphy {
struct device *dev;
void __iomem *glb_base; /* only shared u3 sif */
struct xsphy_instance **phys;
int nphys;
int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
int src_coef; /* coefficient for slew rate calibrate */
};
static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
struct xsphy_instance *inst)
{
void __iomem *pbase = inst->port_base;
int calib_val;
int fm_out;
u32 tmp;
/* use force value */
if (inst->eye_src)
return;
/* enable USB ring oscillator */
tmp = readl(pbase + XSP_USBPHYACR5);
tmp |= P2A5_RG_HSTX_SRCAL_EN;
writel(tmp, pbase + XSP_USBPHYACR5);
udelay(1); /* wait clock stable */
/* enable free run clock */
tmp = readl(pbase + XSP_U2FREQ_FMMONR1);
tmp |= P2F_RG_FRCK_EN;
writel(tmp, pbase + XSP_U2FREQ_FMMONR1);
/* set cycle count as 1024 */
tmp = readl(pbase + XSP_U2FREQ_FMCR0);
tmp &= ~(P2F_RG_CYCLECNT);
tmp |= P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT);
writel(tmp, pbase + XSP_U2FREQ_FMCR0);
/* enable frequency meter */
tmp = readl(pbase + XSP_U2FREQ_FMCR0);
tmp |= P2F_RG_FREQDET_EN;
writel(tmp, pbase + XSP_U2FREQ_FMCR0);
/* ignore return value */
readl_poll_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp,
(tmp & P2F_USB_FM_VALID), 10, 200);
fm_out = readl(pbase + XSP_U2FREQ_MMONR0);
/* disable frequency meter */
tmp = readl(pbase + XSP_U2FREQ_FMCR0);
tmp &= ~P2F_RG_FREQDET_EN;
writel(tmp, pbase + XSP_U2FREQ_FMCR0);
/* disable free run clock */
tmp = readl(pbase + XSP_U2FREQ_FMMONR1);
tmp &= ~P2F_RG_FRCK_EN;
writel(tmp, pbase + XSP_U2FREQ_FMMONR1);
if (fm_out) {
/* (1024 / FM_OUT) x reference clock frequency x coefficient */
tmp = xsphy->src_ref_clk * xsphy->src_coef;
tmp = (tmp * XSP_FM_DET_CYCLE_CNT) / fm_out;
calib_val = DIV_ROUND_CLOSEST(tmp, XSP_SR_COEF_DIVISOR);
} else {
/* if FM detection fail, set default value */
calib_val = 3;
}
dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
inst->index, fm_out, calib_val,
xsphy->src_ref_clk, xsphy->src_coef);
/* set HS slew rate */
tmp = readl(pbase + XSP_USBPHYACR5);
tmp &= ~P2A5_RG_HSTX_SRCTRL;
tmp |= P2A5_RG_HSTX_SRCTRL_VAL(calib_val);
writel(tmp, pbase + XSP_USBPHYACR5);
/* disable USB ring oscillator */
tmp = readl(pbase + XSP_USBPHYACR5);
tmp &= ~P2A5_RG_HSTX_SRCAL_EN;
writel(tmp, pbase + XSP_USBPHYACR5);
}
static void u2_phy_instance_init(struct mtk_xsphy *xsphy,
struct xsphy_instance *inst)
{
void __iomem *pbase = inst->port_base;
u32 tmp;
/* DP/DM BC1.1 path Disable */
tmp = readl(pbase + XSP_USBPHYACR6);
tmp &= ~P2A6_RG_BC11_SW_EN;
writel(tmp, pbase + XSP_USBPHYACR6);
tmp = readl(pbase + XSP_USBPHYACR0);
tmp |= P2A0_RG_INTR_EN;
writel(tmp, pbase + XSP_USBPHYACR0);
}
static void u2_phy_instance_power_on(struct mtk_xsphy *xsphy,
struct xsphy_instance *inst)
{
void __iomem *pbase = inst->port_base;
u32 index = inst->index;
u32 tmp;
tmp = readl(pbase + XSP_USBPHYACR6);
tmp |= P2A6_RG_OTG_VBUSCMP_EN;
writel(tmp, pbase + XSP_USBPHYACR6);
tmp = readl(pbase + XSP_U2PHYDTM1);
tmp |= P2D_RG_VBUSVALID | P2D_RG_AVALID;
tmp &= ~P2D_RG_SESSEND;
writel(tmp, pbase + XSP_U2PHYDTM1);
dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
}
static void u2_phy_instance_power_off(struct mtk_xsphy *xsphy,
struct xsphy_instance *inst)
{
void __iomem *pbase = inst->port_base;
u32 index = inst->index;
u32 tmp;
tmp = readl(pbase + XSP_USBPHYACR6);
tmp &= ~P2A6_RG_OTG_VBUSCMP_EN;
writel(tmp, pbase + XSP_USBPHYACR6);
tmp = readl(pbase + XSP_U2PHYDTM1);
tmp &= ~(P2D_RG_VBUSVALID | P2D_RG_AVALID);
tmp |= P2D_RG_SESSEND;
writel(tmp, pbase + XSP_U2PHYDTM1);
dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
}
static void u2_phy_instance_set_mode(struct mtk_xsphy *xsphy,
struct xsphy_instance *inst,
enum phy_mode mode)
{
u32 tmp;
tmp = readl(inst->port_base + XSP_U2PHYDTM1);
switch (mode) {
case PHY_MODE_USB_DEVICE:
tmp |= P2D_FORCE_IDDIG | P2D_RG_IDDIG;
break;
case PHY_MODE_USB_HOST:
tmp |= P2D_FORCE_IDDIG;
tmp &= ~P2D_RG_IDDIG;
break;
case PHY_MODE_USB_OTG:
tmp &= ~(P2D_FORCE_IDDIG | P2D_RG_IDDIG);
break;
default:
return;
}
writel(tmp, inst->port_base + XSP_U2PHYDTM1);
}
static void phy_parse_property(struct mtk_xsphy *xsphy,
struct xsphy_instance *inst)
{
struct device *dev = &inst->phy->dev;
switch (inst->type) {
case PHY_TYPE_USB2:
device_property_read_u32(dev, "mediatek,efuse-intr",
&inst->efuse_intr);
device_property_read_u32(dev, "mediatek,eye-src",
&inst->eye_src);
device_property_read_u32(dev, "mediatek,eye-vrt",
&inst->eye_vrt);
device_property_read_u32(dev, "mediatek,eye-term",
&inst->eye_term);
dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",
inst->efuse_intr, inst->eye_src,
inst->eye_vrt, inst->eye_term);
break;
case PHY_TYPE_USB3:
device_property_read_u32(dev, "mediatek,efuse-intr",
&inst->efuse_intr);
device_property_read_u32(dev, "mediatek,efuse-tx-imp",
&inst->efuse_tx_imp);
device_property_read_u32(dev, "mediatek,efuse-rx-imp",
&inst->efuse_rx_imp);
dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",
inst->efuse_intr, inst->efuse_tx_imp,
inst->efuse_rx_imp);
break;
default:
dev_err(xsphy->dev, "incompatible phy type\n");
return;
}
}
static void u2_phy_props_set(struct mtk_xsphy *xsphy,
struct xsphy_instance *inst)
{
void __iomem *pbase = inst->port_base;
u32 tmp;
if (inst->efuse_intr) {
tmp = readl(pbase + XSP_USBPHYACR1);
tmp &= ~P2A1_RG_INTR_CAL;
tmp |= P2A1_RG_INTR_CAL_VAL(inst->efuse_intr);
writel(tmp, pbase + XSP_USBPHYACR1);
}
if (inst->eye_src) {
tmp = readl(pbase + XSP_USBPHYACR5);
tmp &= ~P2A5_RG_HSTX_SRCTRL;
tmp |= P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src);
writel(tmp, pbase + XSP_USBPHYACR5);
}
if (inst->eye_vrt) {
tmp = readl(pbase + XSP_USBPHYACR1);
tmp &= ~P2A1_RG_VRT_SEL;
tmp |= P2A1_RG_VRT_SEL_VAL(inst->eye_vrt);
writel(tmp, pbase + XSP_USBPHYACR1);
}
if (inst->eye_term) {
tmp = readl(pbase + XSP_USBPHYACR1);
tmp &= ~P2A1_RG_TERM_SEL;
tmp |= P2A1_RG_TERM_SEL_VAL(inst->eye_term);
writel(tmp, pbase + XSP_USBPHYACR1);
}
}
static void u3_phy_props_set(struct mtk_xsphy *xsphy,
struct xsphy_instance *inst)
{
void __iomem *pbase = inst->port_base;
u32 tmp;
if (inst->efuse_intr) {
tmp = readl(xsphy->glb_base + SSPXTP_PHYA_GLB_00);
tmp &= ~RG_XTP_GLB_BIAS_INTR_CTRL;
tmp |= RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr);
writel(tmp, xsphy->glb_base + SSPXTP_PHYA_GLB_00);
}
if (inst->efuse_tx_imp) {
tmp = readl(pbase + SSPXTP_PHYA_LN_04);
tmp &= ~RG_XTP_LN0_TX_IMPSEL;
tmp |= RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp);
writel(tmp, pbase + SSPXTP_PHYA_LN_04);
}
if (inst->efuse_rx_imp) {
tmp = readl(pbase + SSPXTP_PHYA_LN_14);
tmp &= ~RG_XTP_LN0_RX_IMPSEL;
tmp |= RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp);
writel(tmp, pbase + SSPXTP_PHYA_LN_14);
}
}
static int mtk_phy_init(struct phy *phy)
{
struct xsphy_instance *inst = phy_get_drvdata(phy);
struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
int ret;
ret = clk_prepare_enable(inst->ref_clk);
if (ret) {
dev_err(xsphy->dev, "failed to enable ref_clk\n");
return ret;
}
switch (inst->type) {
case PHY_TYPE_USB2:
u2_phy_instance_init(xsphy, inst);
u2_phy_props_set(xsphy, inst);
break;
case PHY_TYPE_USB3:
u3_phy_props_set(xsphy, inst);
break;
default:
dev_err(xsphy->dev, "incompatible phy type\n");
clk_disable_unprepare(inst->ref_clk);
return -EINVAL;
}
return 0;
}
static int mtk_phy_power_on(struct phy *phy)
{
struct xsphy_instance *inst = phy_get_drvdata(phy);
struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
if (inst->type == PHY_TYPE_USB2) {
u2_phy_instance_power_on(xsphy, inst);
u2_phy_slew_rate_calibrate(xsphy, inst);
}
return 0;
}
static int mtk_phy_power_off(struct phy *phy)
{
struct xsphy_instance *inst = phy_get_drvdata(phy);
struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
if (inst->type == PHY_TYPE_USB2)
u2_phy_instance_power_off(xsphy, inst);
return 0;
}
static int mtk_phy_exit(struct phy *phy)
{
struct xsphy_instance *inst = phy_get_drvdata(phy);
clk_disable_unprepare(inst->ref_clk);
return 0;
}
static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
{
struct xsphy_instance *inst = phy_get_drvdata(phy);
struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
if (inst->type == PHY_TYPE_USB2)
u2_phy_instance_set_mode(xsphy, inst, mode);
return 0;
}
static struct phy *mtk_phy_xlate(struct device *dev,
struct of_phandle_args *args)
{
struct mtk_xsphy *xsphy = dev_get_drvdata(dev);
struct xsphy_instance *inst = NULL;
struct device_node *phy_np = args->np;
int index;
if (args->args_count != 1) {
dev_err(dev, "invalid number of cells in 'phy' property\n");
return ERR_PTR(-EINVAL);
}
for (index = 0; index < xsphy->nphys; index++)
if (phy_np == xsphy->phys[index]->phy->dev.of_node) {
inst = xsphy->phys[index];
break;
}
if (!inst) {
dev_err(dev, "failed to find appropriate phy\n");
return ERR_PTR(-EINVAL);
}
inst->type = args->args[0];
if (!(inst->type == PHY_TYPE_USB2 ||
inst->type == PHY_TYPE_USB3)) {
dev_err(dev, "unsupported phy type: %d\n", inst->type);
return ERR_PTR(-EINVAL);
}
phy_parse_property(xsphy, inst);
return inst->phy;
}
static const struct phy_ops mtk_xsphy_ops = {
.init = mtk_phy_init,
.exit = mtk_phy_exit,
.power_on = mtk_phy_power_on,
.power_off = mtk_phy_power_off,
.set_mode = mtk_phy_set_mode,
.owner = THIS_MODULE,
};
static const struct of_device_id mtk_xsphy_id_table[] = {
{ .compatible = "mediatek,xsphy", },
{ },
};
MODULE_DEVICE_TABLE(of, mtk_xsphy_id_table);
static int mtk_xsphy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *child_np;
struct phy_provider *provider;
struct resource *glb_res;
struct mtk_xsphy *xsphy;
struct resource res;
int port, retval;
xsphy = devm_kzalloc(dev, sizeof(*xsphy), GFP_KERNEL);
if (!xsphy)
return -ENOMEM;
xsphy->nphys = of_get_child_count(np);
xsphy->phys = devm_kcalloc(dev, xsphy->nphys,
sizeof(*xsphy->phys), GFP_KERNEL);
if (!xsphy->phys)
return -ENOMEM;
xsphy->dev = dev;
platform_set_drvdata(pdev, xsphy);
glb_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
/* optional, may not exist if no u3 phys */
if (glb_res) {
/* get banks shared by multiple u3 phys */
xsphy->glb_base = devm_ioremap_resource(dev, glb_res);
if (IS_ERR(xsphy->glb_base)) {
dev_err(dev, "failed to remap glb regs\n");
return PTR_ERR(xsphy->glb_base);
}
}
xsphy->src_ref_clk = XSP_REF_CLK;
xsphy->src_coef = XSP_SLEW_RATE_COEF;
/* update parameters of slew rate calibrate if exist */
device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
&xsphy->src_ref_clk);
device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);
port = 0;
for_each_child_of_node(np, child_np) {
struct xsphy_instance *inst;
struct phy *phy;
inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
if (!inst) {
retval = -ENOMEM;
goto put_child;
}
xsphy->phys[port] = inst;
phy = devm_phy_create(dev, child_np, &mtk_xsphy_ops);
if (IS_ERR(phy)) {
dev_err(dev, "failed to create phy\n");
retval = PTR_ERR(phy);
goto put_child;
}
retval = of_address_to_resource(child_np, 0, &res);
if (retval) {
dev_err(dev, "failed to get address resource(id-%d)\n",
port);
goto put_child;
}
inst->port_base = devm_ioremap_resource(&phy->dev, &res);
if (IS_ERR(inst->port_base)) {
dev_err(dev, "failed to remap phy regs\n");
retval = PTR_ERR(inst->port_base);
goto put_child;
}
inst->phy = phy;
inst->index = port;
phy_set_drvdata(phy, inst);
port++;
inst->ref_clk = devm_clk_get(&phy->dev, "ref");
if (IS_ERR(inst->ref_clk)) {
dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
retval = PTR_ERR(inst->ref_clk);
goto put_child;
}
}
provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
return PTR_ERR_OR_ZERO(provider);
put_child:
of_node_put(child_np);
return retval;
}
static struct platform_driver mtk_xsphy_driver = {
.probe = mtk_xsphy_probe,
.driver = {
.name = "mtk-xsphy",
.of_match_table = mtk_xsphy_id_table,
},
};
module_platform_driver(mtk_xsphy_driver);
MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");
MODULE_LICENSE("GPL v2");
drivers/phy/motorola/phy-mapphone-mdm6600.c
浏览文件 @ 07c4dd34
......@@ -19,6 +19,8 @@
#define PHY_MDM6600_PHY_DELAY_MS 4000 /* PHY enable 2.2s to 3.5s */
#define PHY_MDM6600_ENABLED_DELAY_MS 8000 /* 8s more total for MDM6600 */
#define MDM6600_MODEM_IDLE_DELAY_MS 1000 /* modem after USB suspend */
#define MDM6600_MODEM_WAKE_DELAY_MS 200 /* modem response after idle */
enum phy_mdm6600_ctrl_lines {
PHY_MDM6600_ENABLE, /* USB PHY enable */
......@@ -93,9 +95,11 @@ struct phy_mdm6600 {
struct gpio_descs *cmd_gpios;
struct delayed_work bootup_work;
struct delayed_work status_work;
struct delayed_work modem_wake_work;
struct completion ack;
bool enabled; /* mdm6600 phy enabled */
bool running; /* mdm6600 boot done */
bool awake; /* mdm6600 respnds on n_gsm */
int status;
};
......@@ -446,6 +450,62 @@ static void phy_mdm6600_deferred_power_on(struct work_struct *work)
dev_err(ddata->dev, "Device not functional\n");
}
/*
* USB suspend puts mdm6600 into low power mode. For any n_gsm using apps,
* we need to keep the modem awake by kicking it's mode0 GPIO. This will
* keep the modem awake for about 1.2 seconds. When no n_gsm apps are using
* the modem, runtime PM auto mode can be enabled so modem can enter low
* power mode.
*/
static void phy_mdm6600_wake_modem(struct phy_mdm6600 *ddata)
{
struct gpio_desc *mode_gpio0;
mode_gpio0 = ddata->mode_gpios->desc[PHY_MDM6600_MODE0];
gpiod_set_value_cansleep(mode_gpio0, 1);
usleep_range(5, 15);
gpiod_set_value_cansleep(mode_gpio0, 0);
if (ddata->awake)
usleep_range(5, 15);
else
msleep(MDM6600_MODEM_WAKE_DELAY_MS);
}
static void phy_mdm6600_modem_wake(struct work_struct *work)
{
struct phy_mdm6600 *ddata;
ddata = container_of(work, struct phy_mdm6600, modem_wake_work.work);
phy_mdm6600_wake_modem(ddata);
schedule_delayed_work(&ddata->modem_wake_work,
msecs_to_jiffies(MDM6600_MODEM_IDLE_DELAY_MS));
}
static int __maybe_unused phy_mdm6600_runtime_suspend(struct device *dev)
{
struct phy_mdm6600 *ddata = dev_get_drvdata(dev);
cancel_delayed_work_sync(&ddata->modem_wake_work);
ddata->awake = false;
return 0;
}
static int __maybe_unused phy_mdm6600_runtime_resume(struct device *dev)
{
struct phy_mdm6600 *ddata = dev_get_drvdata(dev);
phy_mdm6600_modem_wake(&ddata->modem_wake_work.work);
ddata->awake = true;
return 0;
}
static const struct dev_pm_ops phy_mdm6600_pm_ops = {
SET_RUNTIME_PM_OPS(phy_mdm6600_runtime_suspend,
phy_mdm6600_runtime_resume, NULL)
};
static const struct of_device_id phy_mdm6600_id_table[] = {
{ .compatible = "motorola,mapphone-mdm6600", },
{},
......@@ -464,6 +524,7 @@ static int phy_mdm6600_probe(struct platform_device *pdev)
INIT_DELAYED_WORK(&ddata->bootup_work,
phy_mdm6600_deferred_power_on);
INIT_DELAYED_WORK(&ddata->status_work, phy_mdm6600_status);
INIT_DELAYED_WORK(&ddata->modem_wake_work, phy_mdm6600_modem_wake);
init_completion(&ddata->ack);
ddata->dev = &pdev->dev;
......@@ -500,6 +561,24 @@ static int phy_mdm6600_probe(struct platform_device *pdev)
*/
msleep(PHY_MDM6600_PHY_DELAY_MS + 500);
/*
* Enable PM runtime only after PHY has been powered up properly.
* It is currently only needed after USB suspends mdm6600 and n_gsm
* needs to access the device. We don't want to do this earlier as
* gpio mode0 pin doubles as mdm6600 wake-up gpio.
*/
pm_runtime_use_autosuspend(ddata->dev);
pm_runtime_set_autosuspend_delay(ddata->dev,
MDM6600_MODEM_IDLE_DELAY_MS);
pm_runtime_enable(ddata->dev);
error = pm_runtime_get_sync(ddata->dev);
if (error < 0) {
dev_warn(ddata->dev, "failed to wake modem: %i\n", error);
pm_runtime_put_noidle(ddata->dev);
}
pm_runtime_mark_last_busy(ddata->dev);
pm_runtime_put_autosuspend(ddata->dev);
return 0;
cleanup:
......@@ -512,6 +591,10 @@ static int phy_mdm6600_remove(struct platform_device *pdev)
struct phy_mdm6600 *ddata = platform_get_drvdata(pdev);
struct gpio_desc *reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET];
pm_runtime_dont_use_autosuspend(ddata->dev);
pm_runtime_put_sync(ddata->dev);
pm_runtime_disable(ddata->dev);
if (!ddata->running)
wait_for_completion_timeout(&ddata->ack,
msecs_to_jiffies(PHY_MDM6600_ENABLED_DELAY_MS));
......@@ -519,6 +602,7 @@ static int phy_mdm6600_remove(struct platform_device *pdev)
gpiod_set_value_cansleep(reset_gpio, 1);
phy_mdm6600_device_power_off(ddata);
cancel_delayed_work_sync(&ddata->modem_wake_work);
cancel_delayed_work_sync(&ddata->bootup_work);
cancel_delayed_work_sync(&ddata->status_work);
......@@ -530,6 +614,7 @@ static struct platform_driver phy_mdm6600_driver = {
.remove = phy_mdm6600_remove,
.driver = {
.name = "phy-mapphone-mdm6600",
.pm = &phy_mdm6600_pm_ops,
.of_match_table = of_match_ptr(phy_mdm6600_id_table),
},
};
......
drivers/phy/phy-core.c
浏览文件 @ 07c4dd34
......@@ -153,6 +153,9 @@ int phy_pm_runtime_get(struct phy *phy)
{
int ret;
if (!phy)
return 0;
if (!pm_runtime_enabled(&phy->dev))
return -ENOTSUPP;
......@@ -168,6 +171,9 @@ int phy_pm_runtime_get_sync(struct phy *phy)
{
int ret;
if (!phy)
return 0;
if (!pm_runtime_enabled(&phy->dev))
return -ENOTSUPP;
......@@ -181,6 +187,9 @@ EXPORT_SYMBOL_GPL(phy_pm_runtime_get_sync);
int phy_pm_runtime_put(struct phy *phy)
{
if (!phy)
return 0;
if (!pm_runtime_enabled(&phy->dev))
return -ENOTSUPP;
......@@ -190,6 +199,9 @@ EXPORT_SYMBOL_GPL(phy_pm_runtime_put);
int phy_pm_runtime_put_sync(struct phy *phy)
{
if (!phy)
return 0;
if (!pm_runtime_enabled(&phy->dev))
return -ENOTSUPP;
......@@ -199,6 +211,9 @@ EXPORT_SYMBOL_GPL(phy_pm_runtime_put_sync);
void phy_pm_runtime_allow(struct phy *phy)
{
if (!phy)
return;
if (!pm_runtime_enabled(&phy->dev))
return;
......@@ -208,6 +223,9 @@ EXPORT_SYMBOL_GPL(phy_pm_runtime_allow);
void phy_pm_runtime_forbid(struct phy *phy)
{
if (!phy)
return;
if (!pm_runtime_enabled(&phy->dev))
return;
......
drivers/phy/qualcomm/Kconfig
浏览文件 @ 07c4dd34
#
# Phy drivers for Qualcomm platforms
# Phy drivers for Qualcomm and Atheros platforms
#
config PHY_ATH79_USB
tristate "Atheros AR71XX/9XXX USB PHY driver"
depends on OF && (ATH79 || COMPILE_TEST)
default y if USB_EHCI_HCD_PLATFORM || USB_OHCI_HCD_PLATFORM
select RESET_CONTROLLER
select GENERIC_PHY
help
Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
config PHY_QCOM_APQ8064_SATA
tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
depends on ARCH_QCOM
......
drivers/phy/qualcomm/Makefile
浏览文件 @ 07c4dd34
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
......
drivers/phy/qualcomm/phy-ath79-usb.c 0 → 100644
浏览文件 @ 07c4dd34
// SPDX-License-Identifier: GPL-2.0+
/*
* Atheros AR71XX/9XXX USB PHY driver
*
* Copyright (C) 2015-2018 Alban Bedel <albeu@free.fr>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/reset.h>
struct ath79_usb_phy {
struct reset_control *reset;
/* The suspend override logic is inverted, hence the no prefix
* to make the code a bit easier to understand.
*/
struct reset_control *no_suspend_override;
};
static int ath79_usb_phy_power_on(struct phy *phy)
{
struct ath79_usb_phy *priv = phy_get_drvdata(phy);
int err = 0;
if (priv->no_suspend_override) {
err = reset_control_assert(priv->no_suspend_override);
if (err)
return err;
}
err = reset_control_deassert(priv->reset);
if (err && priv->no_suspend_override)
reset_control_assert(priv->no_suspend_override);
return err;
}
static int ath79_usb_phy_power_off(struct phy *phy)
{
struct ath79_usb_phy *priv = phy_get_drvdata(phy);
int err = 0;
err = reset_control_assert(priv->reset);
if (err)
return err;
if (priv->no_suspend_override) {
err = reset_control_deassert(priv->no_suspend_override);
if (err)
reset_control_deassert(priv->reset);
}
return err;
}
static const struct phy_ops ath79_usb_phy_ops = {
.power_on = ath79_usb_phy_power_on,
.power_off = ath79_usb_phy_power_off,
.owner = THIS_MODULE,
};
static int ath79_usb_phy_probe(struct platform_device *pdev)
{
struct ath79_usb_phy *priv;
struct phy *phy;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->reset = devm_reset_control_get(&pdev->dev, "usb-phy");
if (IS_ERR(priv->reset))
return PTR_ERR(priv->reset);
priv->no_suspend_override = devm_reset_control_get_optional(
&pdev->dev, "usb-suspend-override");
if (IS_ERR(priv->no_suspend_override))
return PTR_ERR(priv->no_suspend_override);
phy = devm_phy_create(&pdev->dev, NULL, &ath79_usb_phy_ops);
if (IS_ERR(phy))
return PTR_ERR(phy);
phy_set_drvdata(phy, priv);
return PTR_ERR_OR_ZERO(devm_of_phy_provider_register(
&pdev->dev, of_phy_simple_xlate));
}
static const struct of_device_id ath79_usb_phy_of_match[] = {
{ .compatible = "qca,ar7100-usb-phy" },
{}
};
MODULE_DEVICE_TABLE(of, ath79_usb_phy_of_match);
static struct platform_driver ath79_usb_phy_driver = {
.probe = ath79_usb_phy_probe,
.driver = {
.of_match_table = ath79_usb_phy_of_match,
.name = "ath79-usb-phy",
}
};
module_platform_driver(ath79_usb_phy_driver);
MODULE_DESCRIPTION("ATH79 USB PHY driver");
MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
MODULE_LICENSE("GPL");
drivers/phy/qualcomm/phy-qcom-qmp.c
浏览文件 @ 07c4dd34
......@@ -490,6 +490,118 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
/* FLL settings */
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
/* Lock Det settings */
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
};
/* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg {
/* phy-type - PCIE/UFS/USB */
......@@ -766,6 +878,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.has_pwrdn_delay = true,
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
......@@ -774,6 +887,35 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.rx_b_lane_offset = 0x400,
};
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
.serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
.tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
.tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
.rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
.rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
.pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
.clk_list = qmp_v3_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = msm8996_phy_vreg_l,
.num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
.regs = qmp_v3_usb3phy_regs_layout,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.has_pwrdn_delay = true,
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
};
static void qcom_qmp_phy_configure(void __iomem *base,
const unsigned int *regs,
const struct qmp_phy_init_tbl tbl[],
......@@ -793,19 +935,6 @@ static void qcom_qmp_phy_configure(void __iomem *base,
}
}
static int qcom_qmp_phy_poweron(struct phy *phy)
{
struct qmp_phy *qphy = phy_get_drvdata(phy);
struct qcom_qmp *qmp = qphy->qmp;
int ret;
ret = clk_prepare_enable(qphy->pipe_clk);
if (ret)
dev_err(qmp->dev, "pipe_clk enable failed, err=%d\n", ret);
return ret;
}
static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
......@@ -974,6 +1103,12 @@ static int qcom_qmp_phy_init(struct phy *phy)
}
}
ret = clk_prepare_enable(qphy->pipe_clk);
if (ret) {
dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
goto err_clk_enable;
}
/* Tx, Rx, and PCS configurations */
qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
/* Configuration for other LANE for USB-DP combo PHY */
......@@ -1019,6 +1154,8 @@ static int qcom_qmp_phy_init(struct phy *phy)
return ret;
err_pcs_ready:
clk_disable_unprepare(qphy->pipe_clk);
err_clk_enable:
if (cfg->has_lane_rst)
reset_control_assert(qphy->lane_rst);
err_lane_rst:
......@@ -1283,7 +1420,6 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
static const struct phy_ops qcom_qmp_phy_gen_ops = {
.init = qcom_qmp_phy_init,
.exit = qcom_qmp_phy_exit,
.power_on = qcom_qmp_phy_poweron,
.set_mode = qcom_qmp_phy_set_mode,
.owner = THIS_MODULE,
};
......@@ -1381,8 +1517,11 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
.compatible = "qcom,ipq8074-qmp-pcie-phy",
.data = &ipq8074_pciephy_cfg,
}, {
.compatible = "qcom,qmp-v3-usb3-phy",
.compatible = "qcom,sdm845-qmp-usb3-phy",
.data = &qmp_v3_usb3phy_cfg,
}, {
.compatible = "qcom,sdm845-qmp-usb3-uni-phy",
.data = &qmp_v3_usb3_uniphy_cfg,
},
{ },
};
......
drivers/phy/qualcomm/phy-qcom-qmp.h
浏览文件 @ 07c4dd34
......@@ -214,6 +214,8 @@
#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
#define QSERDES_V3_RX_RX_TERM_BW 0x07c
#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
......@@ -227,6 +229,7 @@
#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
#define QSERDES_V3_RX_RX_BAND 0x110
#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
#define QSERDES_V3_RX_RX_MODE_00 0x164
/* Only for QMP V3 PHY - PCS registers */
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
......@@ -273,6 +276,8 @@
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
/* Only for QMP V3 PHY - PCS_MISC registers */
#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
......
drivers/phy/qualcomm/phy-qcom-qusb2.c
浏览文件 @ 07c4dd34
......@@ -20,6 +20,8 @@
#include <linux/reset.h>
#include <linux/slab.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#define QUSB2PHY_PLL_TEST 0x04
#define CLK_REF_SEL BIT(7)
......@@ -60,6 +62,17 @@
#define CORE_RESET BIT(5)
#define CORE_RESET_MUX BIT(6)
/* QUSB2PHY_IMP_CTRL1 register bits */
#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
#define IMP_RES_OFFSET_SHIFT 0x0
/* QUSB2PHY_PORT_TUNE1 register bits */
#define HSTX_TRIM_MASK GENMASK(7, 4)
#define HSTX_TRIM_SHIFT 0x4
#define PREEMPH_WIDTH_HALF_BIT BIT(2)
#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
#define PREEMPHASIS_EN_SHIFT 0x0
#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
#define QUSB2PHY_PLL_CMODE 0x2c
......@@ -139,7 +152,7 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
};
static const unsigned int qusb2_v2_regs_layout[] = {
static const unsigned int sdm845_regs_layout[] = {
[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
[QUSB2PHY_PLL_STATUS] = 0x1a0,
[QUSB2PHY_PORT_TUNE1] = 0x240,
......@@ -153,7 +166,7 @@ static const unsigned int qusb2_v2_regs_layout[] = {
[QUSB2PHY_INTR_CTRL] = 0x230,
};
static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
static const struct qusb2_phy_init_tbl sdm845_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
......@@ -208,10 +221,10 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
.autoresume_en = BIT(3),
};
static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
.tbl = qusb2_v2_init_tbl,
.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
.regs = qusb2_v2_regs_layout,
static const struct qusb2_phy_cfg sdm845_phy_cfg = {
.tbl = sdm845_init_tbl,
.tbl_num = ARRAY_SIZE(sdm845_init_tbl),
.regs = sdm845_regs_layout,
.disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
POWER_DOWN),
......@@ -241,6 +254,15 @@ static const char * const qusb2_phy_vreg_names[] = {
* @tcsr: TCSR syscon register map
* @cell: nvmem cell containing phy tuning value
*
* @override_imp_res_offset: PHY should use different rescode offset
* @imp_res_offset_value: rescode offset to be updated in IMP_CTRL1 register
* @override_hstx_trim: PHY should use different HSTX o/p current value
* @hstx_trim_value: HSTX_TRIM value to be updated in TUNE1 register
* @override_preemphasis: PHY should use different pre-amphasis amplitude
* @preemphasis_level: Amplitude Pre-Emphasis to be updated in TUNE1 register
* @override_preemphasis_width: PHY should use different pre-emphasis duration
* @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
*
* @cfg: phy config data
* @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
* @phy_initialized: indicate if PHY has been initialized
......@@ -259,12 +281,35 @@ struct qusb2_phy {
struct regmap *tcsr;
struct nvmem_cell *cell;
bool override_imp_res_offset;
u8 imp_res_offset_value;
bool override_hstx_trim;
u8 hstx_trim_value;
bool override_preemphasis;
u8 preemphasis_level;
bool override_preemphasis_width;
u8 preemphasis_width;
const struct qusb2_phy_cfg *cfg;
bool has_se_clk_scheme;
bool phy_initialized;
enum phy_mode mode;
};
static inline void qusb2_write_mask(void __iomem *base, u32 offset,
u32 val, u32 mask)
{
u32 reg;
reg = readl(base + offset);
reg &= ~mask;
reg |= val & mask;
writel(reg, base + offset);
/* Ensure above write is completed */
readl(base + offset);
}
static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
{
u32 reg;
......@@ -304,6 +349,42 @@ void qcom_qusb2_phy_configure(void __iomem *base,
}
}
/*
* Update board specific PHY tuning override values if specified from
* device tree.
*/
static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
{
const struct qusb2_phy_cfg *cfg = qphy->cfg;
if (qphy->override_imp_res_offset)
qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT,
IMP_RES_OFFSET_MASK);
if (qphy->override_hstx_trim)
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
qphy->hstx_trim_value << HSTX_TRIM_SHIFT,
HSTX_TRIM_MASK);
if (qphy->override_preemphasis)
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
qphy->preemphasis_level << PREEMPHASIS_EN_SHIFT,
PREEMPHASIS_EN_MASK);
if (qphy->override_preemphasis_width) {
if (qphy->preemphasis_width ==
QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
qusb2_setbits(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE1],
PREEMPH_WIDTH_HALF_BIT);
else
qusb2_clrbits(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE1],
PREEMPH_WIDTH_HALF_BIT);
}
}
/*
* Fetches HS Tx tuning value from nvmem and sets the
* QUSB2PHY_PORT_TUNE1/2 register.
......@@ -315,6 +396,10 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
const struct qusb2_phy_cfg *cfg = qphy->cfg;
u8 *val;
/* efuse register is optional */
if (!qphy->cell)
return;
/*
* Read efuse register having TUNE2/1 parameter's high nibble.
* If efuse register shows value as 0x0, or if we fail to find
......@@ -521,6 +606,9 @@ static int qusb2_phy_init(struct phy *phy)
qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
cfg->tbl_num);
/* Override board specific PHY tuning values */
qusb2_phy_override_phy_params(qphy);
/* Set efuse value for tuning the PHY */
qusb2_phy_set_tune2_param(qphy);
......@@ -643,8 +731,8 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
.compatible = "qcom,msm8996-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
.compatible = "qcom,qusb2-v2-phy",
.data = &qusb2_v2_phy_cfg,
.compatible = "qcom,sdm845-qusb2-phy",
.data = &sdm845_phy_cfg,
},
{ },
};
......@@ -664,6 +752,7 @@ static int qusb2_phy_probe(struct platform_device *pdev)
struct resource *res;
int ret, i;
int num;
u32 value;
qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
if (!qphy)
......@@ -732,6 +821,31 @@ static int qusb2_phy_probe(struct platform_device *pdev)
qphy->cell = NULL;
dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
}
if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
&value)) {
qphy->imp_res_offset_value = (u8)value;
qphy->override_imp_res_offset = true;
}
if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
&value)) {
qphy->hstx_trim_value = (u8)value;
qphy->override_hstx_trim = true;
}
if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
&value)) {
qphy->preemphasis_level = (u8)value;
qphy->override_preemphasis = true;
}
if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
&value)) {
qphy->preemphasis_width = (u8)value;
qphy->override_preemphasis_width = true;
}
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
/*
......
drivers/phy/samsung/phy-exynos-mipi-video.c
浏览文件 @ 07c4dd34
......@@ -231,33 +231,27 @@ struct exynos_mipi_video_phy {
static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
struct exynos_mipi_video_phy *state, unsigned int on)
{
u32 val;
struct regmap *enable_map = state->regmaps[data->enable_map];
struct regmap *resetn_map = state->regmaps[data->resetn_map];
spin_lock(&state->slock);
/* disable in PMU sysreg */
if (!on && data->coupled_phy_id >= 0 &&
state->phys[data->coupled_phy_id].phy->power_count == 0) {
regmap_read(state->regmaps[data->enable_map], data->enable_reg,
&val);
val &= ~data->enable_val;
regmap_write(state->regmaps[data->enable_map], data->enable_reg,
val);
}
state->phys[data->coupled_phy_id].phy->power_count == 0)
regmap_update_bits(enable_map, data->enable_reg,
data->enable_val, 0);
/* PHY reset */
regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
val = on ? (val | data->resetn_val) : (val & ~data->resetn_val);
regmap_write(state->regmaps[data->resetn_map], data->resetn_reg, val);
if (on)
regmap_update_bits(resetn_map, data->resetn_reg,
data->resetn_val, data->resetn_val);
else
regmap_update_bits(resetn_map, data->resetn_reg,
data->resetn_val, 0);
/* enable in PMU sysreg */
if (on) {
regmap_read(state->regmaps[data->enable_map], data->enable_reg,
&val);
val |= data->enable_val;
regmap_write(state->regmaps[data->enable_map], data->enable_reg,
val);
}
if (on)
regmap_update_bits(enable_map, data->enable_reg,
data->enable_val, data->enable_val);
spin_unlock(&state->slock);
......
drivers/phy/st/phy-stm32-usbphyc.c
浏览文件 @ 07c4dd34
......@@ -71,7 +71,6 @@ struct stm32_usbphyc {
struct stm32_usbphyc_phy **phys;
int nphys;
int switch_setup;
bool pll_enabled;
};
static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
......@@ -84,7 +83,8 @@ static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
writel_relaxed(readl_relaxed(reg) & ~bits, reg);
}
static void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
static void stm32_usbphyc_get_pll_params(u32 clk_rate,
struct pll_params *pll_params)
{
unsigned long long fvco, ndiv, frac;
......@@ -271,7 +271,6 @@ static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
struct stm32_usbphyc_phy *usbphyc_phy = NULL;
struct device_node *phynode = args->np;
int port = 0;
for (port = 0; port < usbphyc->nphys; port++) {
......@@ -367,8 +366,8 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
if (IS_ERR(phy)) {
ret = PTR_ERR(phy);
if (ret != -EPROBE_DEFER)
dev_err(dev,
"failed to create phy%d: %d\n", i, ret);
dev_err(dev, "failed to create phy%d: %d\n",
port, ret);
goto put_child;
}
......
drivers/phy/tegra/xusb.c
浏览文件 @ 07c4dd34
......@@ -102,19 +102,6 @@ tegra_xusb_pad_find_phy_node(struct tegra_xusb_pad *pad, unsigned int index)
return np;
}
static int
tegra_xusb_lane_lookup_function(struct tegra_xusb_lane *lane,
const char *function)
{
unsigned int i;
for (i = 0; i < lane->soc->num_funcs; i++)
if (strcmp(function, lane->soc->funcs[i]) == 0)
return i;
return -EINVAL;
}
int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
struct device_node *np)
{
......@@ -126,7 +113,7 @@ int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
if (err < 0)
return err;
err = tegra_xusb_lane_lookup_function(lane, function);
err = match_string(lane->soc->funcs, lane->soc->num_funcs, function);
if (err < 0) {
dev_err(dev, "invalid function \"%s\" for lane \"%s\"\n",
function, np->name);
......
drivers/platform/x86/Kconfig
浏览文件 @ 07c4dd34
......@@ -866,6 +866,7 @@ config ACPI_CMPC
config INTEL_CHT_INT33FE
tristate "Intel Cherry Trail ACPI INT33FE Driver"
depends on X86 && ACPI && I2C && REGULATOR
depends on CHARGER_BQ24190=y || (CHARGER_BQ24190=m && m)
---help---
This driver add support for the INT33FE ACPI device found on
some Intel Cherry Trail devices.
......@@ -877,8 +878,7 @@ config INTEL_CHT_INT33FE
i2c drivers for these chips can bind to the them.
If you enable this driver it is advised to also select
CONFIG_TYPEC_FUSB302=m, CONFIG_CHARGER_BQ24190=m and
CONFIG_BATTERY_MAX17042=m.
CONFIG_TYPEC_FUSB302=m and CONFIG_BATTERY_MAX17042=m.
config INTEL_INT0002_VGPIO
tristate "Intel ACPI INT0002 Virtual GPIO driver"
......
drivers/power/supply/power_supply_core.c
浏览文件 @ 07c4dd34
......@@ -19,6 +19,7 @@
#include <linux/err.h>
#include <linux/of.h>
#include <linux/power_supply.h>
#include <linux/property.h>
#include <linux/thermal.h>
#include "power_supply.h"
......@@ -843,12 +844,21 @@ __power_supply_register(struct device *parent,
{
struct device *dev;
struct power_supply *psy;
int rc;
int i, rc;
if (!parent)
pr_warn("%s: Expected proper parent device for '%s'\n",
__func__, desc->name);
if (!desc || !desc->name || !desc->properties || !desc->num_properties)
return ERR_PTR(-EINVAL);
for (i = 0; i < desc->num_properties; ++i) {
if ((desc->properties[i] == POWER_SUPPLY_PROP_USB_TYPE) &&
(!desc->usb_types || !desc->num_usb_types))
return ERR_PTR(-EINVAL);
}
psy = kzalloc(sizeof(*psy), GFP_KERNEL);
if (!psy)
return ERR_PTR(-ENOMEM);
......@@ -865,7 +875,8 @@ __power_supply_register(struct device *parent,
psy->desc = desc;
if (cfg) {
psy->drv_data = cfg->drv_data;
psy->of_node = cfg->of_node;
psy->of_node =
cfg->fwnode ? to_of_node(cfg->fwnode) : cfg->of_node;
psy->supplied_to = cfg->supplied_to;
psy->num_supplicants = cfg->num_supplicants;
}
......
drivers/power/supply/power_supply_sysfs.c
浏览文件 @ 07c4dd34
......@@ -46,6 +46,11 @@ static const char * const power_supply_type_text[] = {
"USB_PD", "USB_PD_DRP", "BrickID"
};
static const char * const power_supply_usb_type_text[] = {
"Unknown", "SDP", "DCP", "CDP", "ACA", "C",
"PD", "PD_DRP", "PD_PPS", "BrickID"
};
static const char * const power_supply_status_text[] = {
"Unknown", "Charging", "Discharging", "Not charging", "Full"
};
......@@ -73,6 +78,41 @@ static const char * const power_supply_scope_text[] = {
"Unknown", "System", "Device"
};
static ssize_t power_supply_show_usb_type(struct device *dev,
enum power_supply_usb_type *usb_types,
ssize_t num_usb_types,
union power_supply_propval *value,
char *buf)
{
enum power_supply_usb_type usb_type;
ssize_t count = 0;
bool match = false;
int i;
for (i = 0; i < num_usb_types; ++i) {
usb_type = usb_types[i];
if (value->intval == usb_type) {
count += sprintf(buf + count, "[%s] ",
power_supply_usb_type_text[usb_type]);
match = true;
} else {
count += sprintf(buf + count, "%s ",
power_supply_usb_type_text[usb_type]);
}
}
if (!match) {
dev_warn(dev, "driver reporting unsupported connected type\n");
return -EINVAL;
}
if (count)
buf[count - 1] = '\n';
return count;
}
static ssize_t power_supply_show_property(struct device *dev,
struct device_attribute *attr,
char *buf) {
......@@ -115,6 +155,10 @@ static ssize_t power_supply_show_property(struct device *dev,
else if (off == POWER_SUPPLY_PROP_TYPE)
return sprintf(buf, "%s\n",
power_supply_type_text[value.intval]);
else if (off == POWER_SUPPLY_PROP_USB_TYPE)
return power_supply_show_usb_type(dev, psy->desc->usb_types,
psy->desc->num_usb_types,
&value, buf);
else if (off == POWER_SUPPLY_PROP_SCOPE)
return sprintf(buf, "%s\n",
power_supply_scope_text[value.intval]);
......@@ -241,6 +285,7 @@ static struct device_attribute power_supply_attrs[] = {
POWER_SUPPLY_ATTR(time_to_full_now),
POWER_SUPPLY_ATTR(time_to_full_avg),
POWER_SUPPLY_ATTR(type),
POWER_SUPPLY_ATTR(usb_type),
POWER_SUPPLY_ATTR(scope),
POWER_SUPPLY_ATTR(precharge_current),
POWER_SUPPLY_ATTR(charge_term_current),
......
drivers/staging/typec/Kconfig
浏览文件 @ 07c4dd34
......@@ -9,6 +9,14 @@ config TYPEC_TCPCI
help
Type-C Port Controller driver for TCPCI-compliant controller.
config TYPEC_RT1711H
tristate "Richtek RT1711H Type-C chip driver"
select TYPEC_TCPCI
help
Richtek RT1711H Type-C chip driver that works with
Type-C Port Controller Manager to provide USB PD and USB
Type-C functionalities.
endif
endmenu
drivers/staging/typec/Makefile
浏览文件 @ 07c4dd34
obj-$(CONFIG_TYPEC_TCPCI) += tcpci.o
obj-$(CONFIG_TYPEC_RT1711H) += tcpci_rt1711h.o
drivers/staging/typec/tcpci.h
浏览文件 @ 07c4dd34
......@@ -59,6 +59,7 @@
#define TCPC_POWER_CTRL_VCONN_ENABLE BIT(0)
#define TCPC_CC_STATUS 0x1d
#define TCPC_CC_STATUS_TOGGLING BIT(5)
#define TCPC_CC_STATUS_TERM BIT(4)
#define TCPC_CC_STATUS_CC2_SHIFT 2
#define TCPC_CC_STATUS_CC2_MASK 0x3
......
drivers/staging/typec/tcpci_rt1711h.c 0 → 100644
浏览文件 @ 07c4dd34
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, Richtek Technology Corporation
*
* Richtek RT1711H Type-C Chip Driver
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/gpio/consumer.h>
#include <linux/usb/tcpm.h>
#include <linux/regmap.h>
#include "tcpci.h"
#define RT1711H_VID 0x29CF
#define RT1711H_PID 0x1711
#define RT1711H_RTCTRL8 0x9B
/* Autoidle timeout = (tout * 2 + 1) * 6.4ms */
#define RT1711H_RTCTRL8_SET(ck300, ship_off, auto_idle, tout) \
(((ck300) << 7) | ((ship_off) << 5) | \
((auto_idle) << 3) | ((tout) & 0x07))
#define RT1711H_RTCTRL11 0x9E
/* I2C timeout = (tout + 1) * 12.5ms */
#define RT1711H_RTCTRL11_SET(en, tout) \
(((en) << 7) | ((tout) & 0x0F))
#define RT1711H_RTCTRL13 0xA0
#define RT1711H_RTCTRL14 0xA1
#define RT1711H_RTCTRL15 0xA2
#define RT1711H_RTCTRL16 0xA3
struct rt1711h_chip {
struct tcpci_data data;
struct tcpci *tcpci;
struct device *dev;
};
static int rt1711h_read16(struct rt1711h_chip *chip, unsigned int reg, u16 *val)
{
return regmap_raw_read(chip->data.regmap, reg, val, sizeof(u16));
}
static int rt1711h_write16(struct rt1711h_chip *chip, unsigned int reg, u16 val)
{
return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u16));
}
static int rt1711h_read8(struct rt1711h_chip *chip, unsigned int reg, u8 *val)
{
return regmap_raw_read(chip->data.regmap, reg, val, sizeof(u8));
}
static int rt1711h_write8(struct rt1711h_chip *chip, unsigned int reg, u8 val)
{
return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u8));
}
static const struct regmap_config rt1711h_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xFF, /* 0x80 .. 0xFF are vendor defined */
};
static struct rt1711h_chip *tdata_to_rt1711h(struct tcpci_data *tdata)
{
return container_of(tdata, struct rt1711h_chip, data);
}
static int rt1711h_init(struct tcpci *tcpci, struct tcpci_data *tdata)
{
int ret;
struct rt1711h_chip *chip = tdata_to_rt1711h(tdata);
/* CK 300K from 320K, shipping off, auto_idle enable, tout = 32ms */
ret = rt1711h_write8(chip, RT1711H_RTCTRL8,
RT1711H_RTCTRL8_SET(0, 1, 1, 2));
if (ret < 0)
return ret;
/* I2C reset : (val + 1) * 12.5ms */
ret = rt1711h_write8(chip, RT1711H_RTCTRL11,
RT1711H_RTCTRL11_SET(1, 0x0F));
if (ret < 0)
return ret;
/* tTCPCfilter : (26.7 * val) us */
ret = rt1711h_write8(chip, RT1711H_RTCTRL14, 0x0F);
if (ret < 0)
return ret;
/* tDRP : (51.2 + 6.4 * val) ms */
ret = rt1711h_write8(chip, RT1711H_RTCTRL15, 0x04);
if (ret < 0)
return ret;
/* dcSRC.DRP : 33% */
return rt1711h_write16(chip, RT1711H_RTCTRL16, 330);
}
static int rt1711h_set_vconn(struct tcpci *tcpci, struct tcpci_data *tdata,
bool enable)
{
struct rt1711h_chip *chip = tdata_to_rt1711h(tdata);
return rt1711h_write8(chip, RT1711H_RTCTRL8,
RT1711H_RTCTRL8_SET(0, 1, !enable, 2));
}
static int rt1711h_start_drp_toggling(struct tcpci *tcpci,
struct tcpci_data *tdata,
enum typec_cc_status cc)
{
struct rt1711h_chip *chip = tdata_to_rt1711h(tdata);
int ret;
unsigned int reg = 0;
switch (cc) {
default:
case TYPEC_CC_RP_DEF:
reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
case TYPEC_CC_RP_1_5:
reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
case TYPEC_CC_RP_3_0:
reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
}
if (cc == TYPEC_CC_RD)
reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT);
else
reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT);
ret = rt1711h_write8(chip, TCPC_ROLE_CTRL, reg);
if (ret < 0)
return ret;
usleep_range(500, 1000);
return 0;
}
static irqreturn_t rt1711h_irq(int irq, void *dev_id)
{
int ret;
u16 alert;
u8 status;
struct rt1711h_chip *chip = dev_id;
if (!chip->tcpci)
return IRQ_HANDLED;
ret = rt1711h_read16(chip, TCPC_ALERT, &alert);
if (ret < 0)
goto out;
if (alert & TCPC_ALERT_CC_STATUS) {
ret = rt1711h_read8(chip, TCPC_CC_STATUS, &status);
if (ret < 0)
goto out;
/* Clear cc change event triggered by starting toggling */
if (status & TCPC_CC_STATUS_TOGGLING)
rt1711h_write8(chip, TCPC_ALERT, TCPC_ALERT_CC_STATUS);
}
out:
return tcpci_irq(chip->tcpci);
}
static int rt1711h_init_alert(struct rt1711h_chip *chip,
struct i2c_client *client)
{
int ret;
/* Disable chip interrupts before requesting irq */
ret = rt1711h_write16(chip, TCPC_ALERT_MASK, 0);
if (ret < 0)
return ret;
ret = devm_request_threaded_irq(chip->dev, client->irq, NULL,
rt1711h_irq,
IRQF_ONESHOT | IRQF_TRIGGER_LOW,
dev_name(chip->dev), chip);
if (ret < 0)
return ret;
enable_irq_wake(client->irq);
return 0;
}
static int rt1711h_sw_reset(struct rt1711h_chip *chip)
{
int ret;
ret = rt1711h_write8(chip, RT1711H_RTCTRL13, 0x01);
if (ret < 0)
return ret;
usleep_range(1000, 2000);
return 0;
}
static int rt1711h_check_revision(struct i2c_client *i2c)
{
int ret;
ret = i2c_smbus_read_word_data(i2c, TCPC_VENDOR_ID);
if (ret < 0)
return ret;
if (ret != RT1711H_VID) {
dev_err(&i2c->dev, "vid is not correct, 0x%04x\n", ret);
return -ENODEV;
}
ret = i2c_smbus_read_word_data(i2c, TCPC_PRODUCT_ID);
if (ret < 0)
return ret;
if (ret != RT1711H_PID) {
dev_err(&i2c->dev, "pid is not correct, 0x%04x\n", ret);
return -ENODEV;
}
return 0;
}
static int rt1711h_probe(struct i2c_client *client,
const struct i2c_device_id *i2c_id)
{
int ret;
struct rt1711h_chip *chip;
ret = rt1711h_check_revision(client);
if (ret < 0) {
dev_err(&client->dev, "check vid/pid fail\n");
return ret;
}
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->data.regmap = devm_regmap_init_i2c(client,
&rt1711h_regmap_config);
if (IS_ERR(chip->data.regmap))
return PTR_ERR(chip->data.regmap);
chip->dev = &client->dev;
i2c_set_clientdata(client, chip);
ret = rt1711h_sw_reset(chip);
if (ret < 0)
return ret;
ret = rt1711h_init_alert(chip, client);
if (ret < 0)
return ret;
chip->data.init = rt1711h_init;
chip->data.set_vconn = rt1711h_set_vconn;
chip->data.start_drp_toggling = rt1711h_start_drp_toggling;
chip->tcpci = tcpci_register_port(chip->dev, &chip->data);
if (IS_ERR_OR_NULL(chip->tcpci))
return PTR_ERR(chip->tcpci);
return 0;
}
static int rt1711h_remove(struct i2c_client *client)
{
struct rt1711h_chip *chip = i2c_get_clientdata(client);
tcpci_unregister_port(chip->tcpci);
return 0;
}
static const struct i2c_device_id rt1711h_id[] = {
{ "rt1711h", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt1711h_id);
#ifdef CONFIG_OF
static const struct of_device_id rt1711h_of_match[] = {
{ .compatible = "richtek,rt1711h", },
{},
};
MODULE_DEVICE_TABLE(of, rt1711h_of_match);
#endif
static struct i2c_driver rt1711h_i2c_driver = {
.driver = {
.name = "rt1711h",
.of_match_table = of_match_ptr(rt1711h_of_match),
},
.probe = rt1711h_probe,
.remove = rt1711h_remove,
.id_table = rt1711h_id,
};
module_i2c_driver(rt1711h_i2c_driver);
MODULE_AUTHOR("ShuFan Lee <shufan_lee@richtek.com>");
MODULE_DESCRIPTION("RT1711H USB Type-C Port Controller Interface Driver");
MODULE_LICENSE("GPL");
drivers/tty/tty_ioctl.c
浏览文件 @ 07c4dd34
......@@ -290,7 +290,7 @@ EXPORT_SYMBOL(tty_termios_copy_hw);
* between the two termios structures, or a speed change is needed.
*/
int tty_termios_hw_change(struct ktermios *a, struct ktermios *b)
int tty_termios_hw_change(const struct ktermios *a, const struct ktermios *b)
{
if (a->c_ispeed != b->c_ispeed || a->c_ospeed != b->c_ospeed)
return 1;
......
drivers/usb/chipidea/ci.h
浏览文件 @ 07c4dd34
......@@ -450,7 +450,7 @@ void hw_phymode_configure(struct ci_hdrc *ci);
void ci_platform_configure(struct ci_hdrc *ci);
int dbg_create_files(struct ci_hdrc *ci);
void dbg_create_files(struct ci_hdrc *ci);
void dbg_remove_files(struct ci_hdrc *ci);
#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
drivers/usb/chipidea/ci_hdrc_imx.c
浏览文件 @ 07c4dd34
......@@ -291,7 +291,8 @@ static int ci_hdrc_imx_probe(struct platform_device *pdev)
pdata.usb_phy = data->phy;
if (of_device_is_compatible(np, "fsl,imx53-usb") && pdata.usb_phy &&
if ((of_device_is_compatible(np, "fsl,imx53-usb") ||
of_device_is_compatible(np, "fsl,imx51-usb")) && pdata.usb_phy &&
of_usb_get_phy_mode(np) == USBPHY_INTERFACE_MODE_ULPI) {
pdata.flags |= CI_HDRC_OVERRIDE_PHY_CONTROL;
data->override_phy_control = true;
......
drivers/usb/chipidea/core.c
浏览文件 @ 07c4dd34
......@@ -1062,9 +1062,7 @@ static int ci_hdrc_probe(struct platform_device *pdev)
ci_hdrc_otg_fsm_start(ci);
device_set_wakeup_capable(&pdev->dev, true);
ret = dbg_create_files(ci);
if (ret)
goto stop;
dbg_create_files(ci);
ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
if (ret)
......
drivers/usb/chipidea/debug.c
浏览文件 @ 07c4dd34
......@@ -340,54 +340,28 @@ DEFINE_SHOW_ATTRIBUTE(ci_registers);
*
* This function returns an error code
*/
int dbg_create_files(struct ci_hdrc *ci)
void dbg_create_files(struct ci_hdrc *ci)
{
struct dentry *dent;
ci->debugfs = debugfs_create_dir(dev_name(ci->dev), NULL);
if (!ci->debugfs)
return -ENOMEM;
dent = debugfs_create_file("device", S_IRUGO, ci->debugfs, ci,
&ci_device_fops);
if (!dent)
goto err;
dent = debugfs_create_file("port_test", S_IRUGO | S_IWUSR, ci->debugfs,
ci, &ci_port_test_fops);
if (!dent)
goto err;
dent = debugfs_create_file("qheads", S_IRUGO, ci->debugfs, ci,
&ci_qheads_fops);
if (!dent)
goto err;
dent = debugfs_create_file("requests", S_IRUGO, ci->debugfs, ci,
&ci_requests_fops);
if (!dent)
goto err;
debugfs_create_file("device", S_IRUGO, ci->debugfs, ci,
&ci_device_fops);
debugfs_create_file("port_test", S_IRUGO | S_IWUSR, ci->debugfs, ci,
&ci_port_test_fops);
debugfs_create_file("qheads", S_IRUGO, ci->debugfs, ci,
&ci_qheads_fops);
debugfs_create_file("requests", S_IRUGO, ci->debugfs, ci,
&ci_requests_fops);
if (ci_otg_is_fsm_mode(ci)) {
dent = debugfs_create_file("otg", S_IRUGO, ci->debugfs, ci,
&ci_otg_fops);
if (!dent)
goto err;
debugfs_create_file("otg", S_IRUGO, ci->debugfs, ci,
&ci_otg_fops);
}
dent = debugfs_create_file("role", S_IRUGO | S_IWUSR, ci->debugfs, ci,
&ci_role_fops);
if (!dent)
goto err;
dent = debugfs_create_file("registers", S_IRUGO, ci->debugfs, ci,
&ci_registers_fops);
if (dent)
return 0;
err:
debugfs_remove_recursive(ci->debugfs);
return -ENOMEM;
debugfs_create_file("role", S_IRUGO | S_IWUSR, ci->debugfs, ci,
&ci_role_fops);
debugfs_create_file("registers", S_IRUGO, ci->debugfs, ci,
&ci_registers_fops);
}
/**
......
drivers/usb/class/usbtmc.c
浏览文件 @ 07c4dd34
......@@ -21,7 +21,6 @@
#include <linux/usb/tmc.h>
#define RIGOL 1
#define USBTMC_HEADER_SIZE 12
#define USBTMC_MINOR_BASE 176
......@@ -93,8 +92,6 @@ struct usbtmc_device_data {
/* coalesced usb488_caps from usbtmc_dev_capabilities */
__u8 usb488_caps;
u8 rigol_quirk;
/* attributes from the USB TMC spec for this device */
u8 TermChar;
bool TermCharEnabled;
......@@ -110,17 +107,6 @@ struct usbtmc_device_data {
};
#define to_usbtmc_data(d) container_of(d, struct usbtmc_device_data, kref)
struct usbtmc_ID_rigol_quirk {
__u16 idVendor;
__u16 idProduct;
};
static const struct usbtmc_ID_rigol_quirk usbtmc_id_quirk[] = {
{ 0x1ab1, 0x0588 },
{ 0x1ab1, 0x04b0 },
{ 0, 0 }
};
/* Forward declarations */
static struct usb_driver usbtmc_driver;
......@@ -603,16 +589,14 @@ static ssize_t usbtmc_read(struct file *filp, char __user *buf,
goto exit;
}
if (data->rigol_quirk) {
dev_dbg(dev, "usb_bulk_msg_in: count(%zu)\n", count);
dev_dbg(dev, "usb_bulk_msg_in: count(%zu)\n", count);
retval = send_request_dev_dep_msg_in(data, count);
retval = send_request_dev_dep_msg_in(data, count);
if (retval < 0) {
if (data->auto_abort)
usbtmc_ioctl_abort_bulk_out(data);
goto exit;
}
if (retval < 0) {
if (data->auto_abort)
usbtmc_ioctl_abort_bulk_out(data);
goto exit;
}
/* Loop until we have fetched everything we requested */
......@@ -621,23 +605,6 @@ static ssize_t usbtmc_read(struct file *filp, char __user *buf,
done = 0;
while (remaining > 0) {
if (!data->rigol_quirk) {
dev_dbg(dev, "usb_bulk_msg_in: remaining(%zu), count(%zu)\n", remaining, count);
if (remaining > USBTMC_SIZE_IOBUFFER - USBTMC_HEADER_SIZE - 3)
this_part = USBTMC_SIZE_IOBUFFER - USBTMC_HEADER_SIZE - 3;
else
this_part = remaining;
retval = send_request_dev_dep_msg_in(data, this_part);
if (retval < 0) {
dev_err(dev, "usb_bulk_msg returned %d\n", retval);
if (data->auto_abort)
usbtmc_ioctl_abort_bulk_out(data);
goto exit;
}
}
/* Send bulk URB */
retval = usb_bulk_msg(data->usb_dev,
usb_rcvbulkpipe(data->usb_dev,
......@@ -658,7 +625,7 @@ static ssize_t usbtmc_read(struct file *filp, char __user *buf,
}
/* Parse header in first packet */
if ((done == 0) || !data->rigol_quirk) {
if (done == 0) {
/* Sanity checks for the header */
if (actual < USBTMC_HEADER_SIZE) {
dev_err(dev, "Device sent too small first packet: %u < %u\n", actual, USBTMC_HEADER_SIZE);
......@@ -698,20 +665,11 @@ static ssize_t usbtmc_read(struct file *filp, char __user *buf,
actual -= USBTMC_HEADER_SIZE;
/* Check if the message is smaller than requested */
if (data->rigol_quirk) {
if (remaining > n_characters)
remaining = n_characters;
/* Remove padding if it exists */
if (actual > remaining)
actual = remaining;
}
else {
if (this_part > n_characters)
this_part = n_characters;
/* Remove padding if it exists */
if (actual > this_part)
actual = this_part;
}
if (remaining > n_characters)
remaining = n_characters;
/* Remove padding if it exists */
if (actual > remaining)
actual = remaining;
dev_dbg(dev, "Bulk-IN header: N_characters(%u), bTransAttr(%u)\n", n_characters, buffer[8]);
......@@ -1365,7 +1323,6 @@ static int usbtmc_probe(struct usb_interface *intf,
struct usbtmc_device_data *data;
struct usb_host_interface *iface_desc;
struct usb_endpoint_descriptor *bulk_in, *bulk_out, *int_in;
int n;
int retcode;
dev_dbg(&intf->dev, "%s called\n", __func__);
......@@ -1385,20 +1342,6 @@ static int usbtmc_probe(struct usb_interface *intf,
atomic_set(&data->srq_asserted, 0);
data->zombie = 0;
/* Determine if it is a Rigol or not */
data->rigol_quirk = 0;
dev_dbg(&intf->dev, "Trying to find if device Vendor 0x%04X Product 0x%04X has the RIGOL quirk\n",
le16_to_cpu(data->usb_dev->descriptor.idVendor),
le16_to_cpu(data->usb_dev->descriptor.idProduct));
for(n = 0; usbtmc_id_quirk[n].idVendor > 0; n++) {
if ((usbtmc_id_quirk[n].idVendor == le16_to_cpu(data->usb_dev->descriptor.idVendor)) &&
(usbtmc_id_quirk[n].idProduct == le16_to_cpu(data->usb_dev->descriptor.idProduct))) {
dev_dbg(&intf->dev, "Setting this device as having the RIGOL quirk\n");
data->rigol_quirk = 1;
break;
}
}
/* Initialize USBTMC bTag and other fields */
data->bTag = 1;
data->TermCharEnabled = 0;
......
drivers/usb/core/hcd.c
浏览文件 @ 07c4dd34
......@@ -33,7 +33,6 @@
#include <linux/phy/phy.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
#include <linux/usb/phy.h>
#include <linux/usb/otg.h>
#include "usb.h"
......@@ -568,6 +567,7 @@ static int rh_call_control (struct usb_hcd *hcd, struct urb *urb)
switch (wValue & 0xff00) {
case USB_DT_DEVICE << 8:
switch (hcd->speed) {
case HCD_USB32:
case HCD_USB31:
bufp = usb31_rh_dev_descriptor;
break;
......@@ -592,6 +592,7 @@ static int rh_call_control (struct usb_hcd *hcd, struct urb *urb)
break;
case USB_DT_CONFIG << 8:
switch (hcd->speed) {
case HCD_USB32:
case HCD_USB31:
case HCD_USB3:
bufp = ss_rh_config_descriptor;
......@@ -2742,34 +2743,14 @@ int usb_add_hcd(struct usb_hcd *hcd,
int retval;
struct usb_device *rhdev;
if (IS_ENABLED(CONFIG_USB_PHY) && !hcd->skip_phy_initialization) {
struct usb_phy *phy = usb_get_phy_dev(hcd->self.sysdev, 0);
if (IS_ERR(phy)) {
retval = PTR_ERR(phy);
if (retval == -EPROBE_DEFER)
return retval;
} else {
retval = usb_phy_init(phy);
if (retval) {
usb_put_phy(phy);
return retval;
}
hcd->usb_phy = phy;
hcd->remove_phy = 1;
}
}
if (!hcd->skip_phy_initialization && usb_hcd_is_primary_hcd(hcd)) {
hcd->phy_roothub = usb_phy_roothub_alloc(hcd->self.sysdev);
if (IS_ERR(hcd->phy_roothub)) {
retval = PTR_ERR(hcd->phy_roothub);
goto err_phy_roothub_alloc;
}
if (IS_ERR(hcd->phy_roothub))
return PTR_ERR(hcd->phy_roothub);
retval = usb_phy_roothub_init(hcd->phy_roothub);
if (retval)
goto err_phy_roothub_alloc;
return retval;
retval = usb_phy_roothub_power_on(hcd->phy_roothub);
if (retval)
......@@ -2819,6 +2800,9 @@ int usb_add_hcd(struct usb_hcd *hcd,
hcd->self.root_hub = rhdev;
mutex_unlock(&usb_port_peer_mutex);
rhdev->rx_lanes = 1;
rhdev->tx_lanes = 1;
switch (hcd->speed) {
case HCD_USB11:
rhdev->speed = USB_SPEED_FULL;
......@@ -2832,6 +2816,10 @@ int usb_add_hcd(struct usb_hcd *hcd,
case HCD_USB3:
rhdev->speed = USB_SPEED_SUPER;
break;
case HCD_USB32:
rhdev->rx_lanes = 2;
rhdev->tx_lanes = 2;
/* fall through */
case HCD_USB31:
rhdev->speed = USB_SPEED_SUPER_PLUS;
break;
......@@ -2943,12 +2931,7 @@ int usb_add_hcd(struct usb_hcd *hcd,
usb_phy_roothub_power_off(hcd->phy_roothub);
err_usb_phy_roothub_power_on:
usb_phy_roothub_exit(hcd->phy_roothub);
err_phy_roothub_alloc:
if (hcd->remove_phy && hcd->usb_phy) {
usb_phy_shutdown(hcd->usb_phy);
usb_put_phy(hcd->usb_phy);
hcd->usb_phy = NULL;
}
return retval;
}
EXPORT_SYMBOL_GPL(usb_add_hcd);
......@@ -3024,12 +3007,6 @@ void usb_remove_hcd(struct usb_hcd *hcd)
usb_phy_roothub_power_off(hcd->phy_roothub);
usb_phy_roothub_exit(hcd->phy_roothub);
if (hcd->remove_phy && hcd->usb_phy) {
usb_phy_shutdown(hcd->usb_phy);
usb_put_phy(hcd->usb_phy);
hcd->usb_phy = NULL;
}
usb_put_invalidate_rhdev(hcd);
hcd->flags = 0;
}
......
drivers/usb/core/hub.c
浏览文件 @ 07c4dd34
......@@ -2636,7 +2636,7 @@ static unsigned hub_is_wusb(struct usb_hub *hub)
#define SET_ADDRESS_TRIES 2
#define GET_DESCRIPTOR_TRIES 2
#define SET_CONFIG_TRIES (2 * (use_both_schemes + 1))
#define USE_NEW_SCHEME(i) ((i) / 2 == (int)old_scheme_first)
#define USE_NEW_SCHEME(i, scheme) ((i) / 2 == (int)scheme)
#define HUB_ROOT_RESET_TIME 60 /* times are in msec */
#define HUB_SHORT_RESET_TIME 10
......@@ -2651,12 +2651,16 @@ static unsigned hub_is_wusb(struct usb_hub *hub)
* enumeration failures, so disable this enumeration scheme for USB3
* devices.
*/
static bool use_new_scheme(struct usb_device *udev, int retry)
static bool use_new_scheme(struct usb_device *udev, int retry,
struct usb_port *port_dev)
{
int old_scheme_first_port =
port_dev->quirks & USB_PORT_QUIRK_OLD_SCHEME;
if (udev->speed >= USB_SPEED_SUPER)
return false;
return USE_NEW_SCHEME(retry);
return USE_NEW_SCHEME(retry, old_scheme_first_port || old_scheme_first);
}
/* Is a USB 3.0 port in the Inactive or Compliance Mode state?
......@@ -2751,6 +2755,14 @@ static int hub_port_wait_reset(struct usb_hub *hub, int port1,
if (!udev)
return 0;
if (hub_is_superspeedplus(hub->hdev)) {
/* extended portstatus Rx and Tx lane count are zero based */
udev->rx_lanes = USB_EXT_PORT_RX_LANES(ext_portstatus) + 1;
udev->tx_lanes = USB_EXT_PORT_TX_LANES(ext_portstatus) + 1;
} else {
udev->rx_lanes = 1;
udev->tx_lanes = 1;
}
if (hub_is_wusb(hub))
udev->speed = USB_SPEED_WIRELESS;
else if (hub_is_superspeedplus(hub->hdev) &&
......@@ -2867,7 +2879,11 @@ static int hub_port_reset(struct usb_hub *hub, int port1,
done:
if (status == 0) {
/* TRSTRCY = 10 ms; plus some extra */
msleep(10 + 40);
if (port_dev->quirks & USB_PORT_QUIRK_FAST_ENUM)
usleep_range(10000, 12000);
else
msleep(10 + 40);
if (udev) {
struct usb_hcd *hcd = bus_to_hcd(udev->bus);
......@@ -3376,6 +3392,10 @@ static int wait_for_connected(struct usb_device *udev,
while (delay_ms < 2000) {
if (status || *portstatus & USB_PORT_STAT_CONNECTION)
break;
if (!port_is_power_on(hub, *portstatus)) {
status = -ENODEV;
break;
}
msleep(20);
delay_ms += 20;
status = hub_port_status(hub, *port1, portstatus, portchange);
......@@ -4380,6 +4400,7 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1,
{
struct usb_device *hdev = hub->hdev;
struct usb_hcd *hcd = bus_to_hcd(hdev->bus);
struct usb_port *port_dev = hub->ports[port1 - 1];
int retries, operations, retval, i;
unsigned delay = HUB_SHORT_RESET_TIME;
enum usb_device_speed oldspeed = udev->speed;
......@@ -4501,7 +4522,7 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1,
for (retries = 0; retries < GET_DESCRIPTOR_TRIES; (++retries, msleep(100))) {
bool did_new_scheme = false;
if (use_new_scheme(udev, retry_counter)) {
if (use_new_scheme(udev, retry_counter, port_dev)) {
struct usb_device_descriptor *buf;
int r = 0;
......@@ -4551,7 +4572,9 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1,
* reset. But only on the first attempt,
* lest we get into a time out/reset loop
*/
if (r == 0 || (r == -ETIMEDOUT && retries == 0))
if (r == 0 || (r == -ETIMEDOUT &&
retries == 0 &&
udev->speed > USB_SPEED_FULL))
break;
}
udev->descriptor.bMaxPacketSize0 =
......@@ -4598,9 +4621,12 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1,
if (udev->speed >= USB_SPEED_SUPER) {
devnum = udev->devnum;
dev_info(&udev->dev,
"%s SuperSpeed%s USB device number %d using %s\n",
"%s SuperSpeed%s%s USB device number %d using %s\n",
(udev->config) ? "reset" : "new",
(udev->speed == USB_SPEED_SUPER_PLUS) ? "Plus" : "",
(udev->speed == USB_SPEED_SUPER_PLUS) ?
"Plus Gen 2" : " Gen 1",
(udev->rx_lanes == 2 && udev->tx_lanes == 2) ?
"x2" : "",
devnum, driver_name);
}
......
drivers/usb/core/hub.h
浏览文件 @ 07c4dd34
......@@ -98,6 +98,7 @@ struct usb_port {
struct mutex status_lock;
u32 over_current_count;
u8 portnum;
u32 quirks;
unsigned int is_superspeed:1;
unsigned int usb3_lpm_u1_permit:1;
unsigned int usb3_lpm_u2_permit:1;
......
drivers/usb/core/message.c
浏览文件 @ 07c4dd34
......@@ -940,7 +940,7 @@ int usb_set_isoch_delay(struct usb_device *dev)
return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
USB_REQ_SET_ISOCH_DELAY,
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
cpu_to_le16(dev->hub_delay), 0, NULL, 0,
dev->hub_delay, 0, NULL, 0,
USB_CTRL_SET_TIMEOUT);
}
......
drivers/usb/core/port.c
浏览文件 @ 07c4dd34
......@@ -50,6 +50,28 @@ static ssize_t over_current_count_show(struct device *dev,
}
static DEVICE_ATTR_RO(over_current_count);
static ssize_t quirks_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_port *port_dev = to_usb_port(dev);
return sprintf(buf, "%08x\n", port_dev->quirks);
}
static ssize_t quirks_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct usb_port *port_dev = to_usb_port(dev);
u32 value;
if (kstrtou32(buf, 16, &value))
return -EINVAL;
port_dev->quirks = value;
return count;
}
static DEVICE_ATTR_RW(quirks);
static ssize_t usb3_lpm_permit_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
......@@ -118,6 +140,7 @@ static DEVICE_ATTR_RW(usb3_lpm_permit);
static struct attribute *port_dev_attrs[] = {
&dev_attr_connect_type.attr,
&dev_attr_quirks.attr,
&dev_attr_over_current_count.attr,
NULL,
};
......
drivers/usb/core/sysfs.c
浏览文件 @ 07c4dd34
......@@ -175,6 +175,26 @@ static ssize_t speed_show(struct device *dev, struct device_attribute *attr,
}
static DEVICE_ATTR_RO(speed);
static ssize_t rx_lanes_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct usb_device *udev;
udev = to_usb_device(dev);
return sprintf(buf, "%d\n", udev->rx_lanes);
}
static DEVICE_ATTR_RO(rx_lanes);
static ssize_t tx_lanes_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct usb_device *udev;
udev = to_usb_device(dev);
return sprintf(buf, "%d\n", udev->tx_lanes);
}
static DEVICE_ATTR_RO(tx_lanes);
static ssize_t busnum_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
......@@ -790,6 +810,8 @@ static struct attribute *dev_attrs[] = {
&dev_attr_bNumConfigurations.attr,
&dev_attr_bMaxPacketSize0.attr,
&dev_attr_speed.attr,
&dev_attr_rx_lanes.attr,
&dev_attr_tx_lanes.attr,
&dev_attr_busnum.attr,
&dev_attr_devnum.attr,
&dev_attr_devpath.attr,
......
drivers/usb/core/usb.c
浏览文件 @ 07c4dd34
......@@ -1167,30 +1167,16 @@ static struct notifier_block usb_bus_nb = {
struct dentry *usb_debug_root;
EXPORT_SYMBOL_GPL(usb_debug_root);
static struct dentry *usb_debug_devices;
static int usb_debugfs_init(void)
static void usb_debugfs_init(void)
{
usb_debug_root = debugfs_create_dir("usb", NULL);
if (!usb_debug_root)
return -ENOENT;
usb_debug_devices = debugfs_create_file("devices", 0444,
usb_debug_root, NULL,
&usbfs_devices_fops);
if (!usb_debug_devices) {
debugfs_remove(usb_debug_root);
usb_debug_root = NULL;
return -ENOENT;
}
return 0;
debugfs_create_file("devices", 0444, usb_debug_root, NULL,
&usbfs_devices_fops);
}
static void usb_debugfs_cleanup(void)
{
debugfs_remove(usb_debug_devices);
debugfs_remove(usb_debug_root);
debugfs_remove_recursive(usb_debug_root);
}
/*
......@@ -1205,9 +1191,7 @@ static int __init usb_init(void)
}
usb_init_pool_max();
retval = usb_debugfs_init();
if (retval)
goto out;
usb_debugfs_init();
usb_acpi_register();
retval = bus_register(&usb_bus_type);
......
drivers/usb/dwc2/core.c
浏览文件 @ 07c4dd34
......@@ -419,6 +419,8 @@ static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
/**
* dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
* filter is enabled.
*
* @hsotg: Programming view of DWC_otg controller
*/
static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
{
......@@ -564,6 +566,9 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
* If a force is done, it requires a IDDIG debounce filter delay if
* the filter is configured and enabled. We poll the current mode of
* the controller to account for this delay.
*
* @hsotg: Programming view of DWC_otg controller
* @host: Host mode flag
*/
void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
{
......@@ -610,6 +615,8 @@ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
* or not because the value of the connector ID status is affected by
* the force mode. We only need to call this once during probe if
* dr_mode == OTG.
*
* @hsotg: Programming view of DWC_otg controller
*/
static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
{
......
drivers/usb/dwc2/core.h
浏览文件 @ 07c4dd34
......@@ -164,12 +164,11 @@ struct dwc2_hsotg_req;
* and has yet to be completed (maybe due to data move, or simply
* awaiting an ack from the core all the data has been completed).
* @debugfs: File entry for debugfs file for this endpoint.
* @lock: State lock to protect contents of endpoint.
* @dir_in: Set to true if this endpoint is of the IN direction, which
* means that it is sending data to the Host.
* @index: The index for the endpoint registers.
* @mc: Multi Count - number of transactions per microframe
* @interval - Interval for periodic endpoints, in frames or microframes.
* @interval: Interval for periodic endpoints, in frames or microframes.
* @name: The name array passed to the USB core.
* @halted: Set if the endpoint has been halted.
* @periodic: Set if this is a periodic ep, such as Interrupt
......@@ -178,10 +177,11 @@ struct dwc2_hsotg_req;
* @desc_list_dma: The DMA address of descriptor chain currently in use.
* @desc_list: Pointer to descriptor DMA chain head currently in use.
* @desc_count: Count of entries within the DMA descriptor chain of EP.
* @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1.
* @next_desc: index of next free descriptor in the ISOC chain under SW control.
* @compl_desc: index of next descriptor to be completed by xFerComplete
* @total_data: The total number of data bytes done.
* @fifo_size: The size of the FIFO (for periodic IN endpoints)
* @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
* @fifo_load: The amount of data loaded into the FIFO (periodic IN)
* @last_load: The offset of data for the last start of request.
* @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
......@@ -231,8 +231,8 @@ struct dwc2_hsotg_ep {
struct dwc2_dma_desc *desc_list;
u8 desc_count;
unsigned char isoc_chain_num;
unsigned int next_desc;
unsigned int compl_desc;
char name[10];
};
......@@ -380,6 +380,12 @@ enum dwc2_ep0_state {
* is FS.
* 0 - No (default)
* 1 - Yes
* @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
* 0 - Disable (default)
* 1 - Enable
* @acg_enable: For enabling Active Clock Gating in the controller
* 0 - No
* 1 - Yes
* @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
* 0 - No (default)
* 1 - Yes
......@@ -511,6 +517,7 @@ struct dwc2_core_params {
bool hird_threshold_en;
u8 hird_threshold;
bool activate_stm_fs_transceiver;
bool ipg_isoc_en;
u16 max_packet_count;
u32 max_transfer_size;
u32 ahbcfg;
......@@ -548,7 +555,7 @@ struct dwc2_core_params {
*
* The values that are not in dwc2_core_params are documented below.
*
* @op_mode Mode of Operation
* @op_mode: Mode of Operation
* 0 - HNP- and SRP-Capable OTG (Host & Device)
* 1 - SRP-Capable OTG (Host & Device)
* 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
......@@ -556,43 +563,102 @@ struct dwc2_core_params {
* 4 - Non-OTG Device
* 5 - SRP-Capable Host
* 6 - Non-OTG Host
* @arch Architecture
* @arch: Architecture
* 0 - Slave only
* 1 - External DMA
* 2 - Internal DMA
* @power_optimized Are power optimizations enabled?
* @num_dev_ep Number of device endpoints available
* @num_dev_in_eps Number of device IN endpoints available
* @num_dev_perio_in_ep Number of device periodic IN endpoints
* available
* @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
* @ipg_isoc_en: This feature indicates that the controller supports
* the worst-case scenario of Rx followed by Rx
* Interpacket Gap (IPG) (32 bitTimes) as per the utmi
* specification for any token following ISOC OUT token.
* 0 - Don't support
* 1 - Support
* @power_optimized: Are power optimizations enabled?
* @num_dev_ep: Number of device endpoints available
* @num_dev_in_eps: Number of device IN endpoints available
* @num_dev_perio_in_ep: Number of device periodic IN endpoints
* available
* @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
* Depth
* 0 to 30
* @host_perio_tx_q_depth
* @host_perio_tx_q_depth:
* Host Mode Periodic Request Queue Depth
* 2, 4 or 8
* @nperio_tx_q_depth
* @nperio_tx_q_depth:
* Non-Periodic Request Queue Depth
* 2, 4 or 8
* @hs_phy_type High-speed PHY interface type
* @hs_phy_type: High-speed PHY interface type
* 0 - High-speed interface not supported
* 1 - UTMI+
* 2 - ULPI
* 3 - UTMI+ and ULPI
* @fs_phy_type Full-speed PHY interface type
* @fs_phy_type: Full-speed PHY interface type
* 0 - Full speed interface not supported
* 1 - Dedicated full speed interface
* 2 - FS pins shared with UTMI+ pins
* 3 - FS pins shared with ULPI pins
* @total_fifo_size: Total internal RAM for FIFOs (bytes)
* @hibernation Is hibernation enabled?
* @utmi_phy_data_width UTMI+ PHY data width
* @hibernation: Is hibernation enabled?
* @utmi_phy_data_width: UTMI+ PHY data width
* 0 - 8 bits
* 1 - 16 bits
* 2 - 8 or 16 bits
* @snpsid: Value from SNPSID register
* @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
* @g_tx_fifo_size[] Power-on values of TxFIFO sizes
* @g_tx_fifo_size: Power-on values of TxFIFO sizes
* @dma_desc_enable: When DMA mode is enabled, specifies whether to use
* address DMA mode or descriptor DMA mode for accessing
* the data FIFOs. The driver will automatically detect the
* value for this if none is specified.
* 0 - Address DMA
* 1 - Descriptor DMA (default, if available)
* @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
* 1 - Allow dynamic FIFO sizing (default, if available)
* @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
* are enabled for non-periodic IN endpoints in device
* mode.
* @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
* in host mode when dynamic FIFO sizing is enabled
* 16 to 32768
* Actual maximum value is autodetected and also
* the default.
* @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
* host mode when dynamic FIFO sizing is enabled
* 16 to 32768
* Actual maximum value is autodetected and also
* the default.
* @max_transfer_size: The maximum transfer size supported, in bytes
* 2047 to 65,535
* Actual maximum value is autodetected and also
* the default.
* @max_packet_count: The maximum number of packets in a transfer
* 15 to 511
* Actual maximum value is autodetected and also
* the default.
* @host_channels: The number of host channel registers to use
* 1 to 16
* Actual maximum value is autodetected and also
* the default.
* @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
* in device mode when dynamic FIFO sizing is enabled
* 16 to 32768
* Actual maximum value is autodetected and also
* the default.
* @i2c_enable: Specifies whether to use the I2Cinterface for a full
* speed PHY. This parameter is only applicable if phy_type
* is FS.
* 0 - No (default)
* 1 - Yes
* @acg_enable: For enabling Active Clock Gating in the controller
* 0 - Disable
* 1 - Enable
* @lpm_mode: For enabling Link Power Management in the controller
* 0 - Disable
* 1 - Enable
* @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
* FIFO sizing is enabled 16 to 32768
* Actual maximum value is autodetected and also
* the default.
*/
struct dwc2_hw_params {
unsigned op_mode:3;
......@@ -622,6 +688,7 @@ struct dwc2_hw_params {
unsigned hibernation:1;
unsigned utmi_phy_data_width:2;
unsigned lpm_mode:1;
unsigned ipg_isoc_en:1;
u32 snpsid;
u32 dev_ep_dirs;
u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
......@@ -642,7 +709,11 @@ struct dwc2_hw_params {
* @gi2cctl: Backup of GI2CCTL register
* @glpmcfg: Backup of GLPMCFG register
* @gdfifocfg: Backup of GDFIFOCFG register
* @pcgcctl: Backup of PCGCCTL register
* @pcgcctl1: Backup of PCGCCTL1 register
* @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
* @gpwrdn: Backup of GPWRDN register
* @valid: True if registers values backuped.
*/
struct dwc2_gregs_backup {
u32 gotgctl;
......@@ -675,6 +746,7 @@ struct dwc2_gregs_backup {
* @doeptsiz: Backup of DOEPTSIZ register
* @doepdma: Backup of DOEPDMA register
* @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
* @valid: True if registers values backuped.
*/
struct dwc2_dregs_backup {
u32 dcfg;
......@@ -698,9 +770,10 @@ struct dwc2_dregs_backup {
* @hcfg: Backup of HCFG register
* @haintmsk: Backup of HAINTMSK register
* @hcintmsk: Backup of HCINTMSK register
* @hptr0: Backup of HPTR0 register
* @hprt0: Backup of HPTR0 register
* @hfir: Backup of HFIR register
* @hptxfsiz: Backup of HPTXFSIZ register
* @valid: True if registers values backuped.
*/
struct dwc2_hregs_backup {
u32 hcfg;
......@@ -800,7 +873,7 @@ struct dwc2_hregs_backup {
* @regs: Pointer to controller regs
* @hw_params: Parameters that were autodetected from the
* hardware registers
* @core_params: Parameters that define how the core should be configured
* @params: Parameters that define how the core should be configured
* @op_state: The operational State, during transitions (a_host=>
* a_peripheral and b_device=>b_host) this may not match
* the core, but allows the software to determine
......@@ -809,10 +882,13 @@ struct dwc2_hregs_backup {
* - USB_DR_MODE_PERIPHERAL
* - USB_DR_MODE_HOST
* - USB_DR_MODE_OTG
* @hcd_enabled Host mode sub-driver initialization indicator.
* @gadget_enabled Peripheral mode sub-driver initialization indicator.
* @ll_hw_enabled Status of low-level hardware resources.
* @hcd_enabled: Host mode sub-driver initialization indicator.
* @gadget_enabled: Peripheral mode sub-driver initialization indicator.
* @ll_hw_enabled: Status of low-level hardware resources.
* @hibernated: True if core is hibernated
* @frame_number: Frame number read from the core. For both device
* and host modes. The value ranges are from 0
* to HFNUM_MAX_FRNUM.
* @phy: The otg phy transceiver structure for phy control.
* @uphy: The otg phy transceiver structure for old USB phy
* control.
......@@ -832,13 +908,25 @@ struct dwc2_hregs_backup {
* interrupt
* @wkp_timer: Timer object for handling Wakeup Detected interrupt
* @lx_state: Lx state of connected device
* @gregs_backup: Backup of global registers during suspend
* @dregs_backup: Backup of device registers during suspend
* @hregs_backup: Backup of host registers during suspend
* @gr_backup: Backup of global registers during suspend
* @dr_backup: Backup of device registers during suspend
* @hr_backup: Backup of host registers during suspend
*
* These are for host mode:
*
* @flags: Flags for handling root port state changes
* @flags.d32: Contain all root port flags
* @flags.b: Separate root port flags from each other
* @flags.b.port_connect_status_change: True if root port connect status
* changed
* @flags.b.port_connect_status: True if device connected to root port
* @flags.b.port_reset_change: True if root port reset status changed
* @flags.b.port_enable_change: True if root port enable status changed
* @flags.b.port_suspend_change: True if root port suspend status changed
* @flags.b.port_over_current_change: True if root port over current state
* changed.
* @flags.b.port_l1_change: True if root port l1 status changed
* @flags.b.reserved: Reserved bits of root port register
* @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
* Transfers associated with these QHs are not currently
* assigned to a host channel.
......@@ -847,6 +935,9 @@ struct dwc2_hregs_backup {
* assigned to a host channel.
* @non_periodic_qh_ptr: Pointer to next QH to process in the active
* non-periodic schedule
* @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
* Transfers associated with these QHs are not currently
* assigned to a host channel.
* @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
* list of QHs for periodic transfers that are _not_
* scheduled for the next frame. Each QH in the list has an
......@@ -886,8 +977,6 @@ struct dwc2_hregs_backup {
* @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
* host is in high speed mode; low speed schedules are
* stored elsewhere since we need one per TT.
* @frame_number: Frame number read from the core at SOF. The value ranges
* from 0 to HFNUM_MAX_FRNUM.
* @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
* SOF enable/disable.
* @free_hc_list: Free host channels in the controller. This is a list of
......@@ -898,8 +987,8 @@ struct dwc2_hregs_backup {
* host channel is available for non-periodic transactions.
* @non_periodic_channels: Number of host channels assigned to non-periodic
* transfers
* @available_host_channels Number of host channels available for the microframe
* scheduler to use
* @available_host_channels: Number of host channels available for the
* microframe scheduler to use
* @hc_ptr_array: Array of pointers to the host channel descriptors.
* Allows accessing a host channel descriptor given the
* host channel number. This is useful in interrupt
......@@ -922,9 +1011,6 @@ struct dwc2_hregs_backup {
* @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
* @num_of_eps: Number of available EPs (excluding EP0)
* @debug_root: Root directrory for debugfs.
* @debug_file: Main status file for debugfs.
* @debug_testmode: Testmode status file for debugfs.
* @debug_fifo: FIFO status file for debugfs.
* @ep0_reply: Request used for ep0 reply.
* @ep0_buff: Buffer for EP0 reply data, if needed.
* @ctrl_buff: Buffer for EP0 control requests.
......@@ -939,7 +1025,37 @@ struct dwc2_hregs_backup {
* @ctrl_in_desc: EP0 IN data phase desc chain pointer
* @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
* @ctrl_out_desc: EP0 OUT data phase desc chain pointer
* @eps: The endpoints being supplied to the gadget framework
* @irq: Interrupt request line number
* @clk: Pointer to otg clock
* @reset: Pointer to dwc2 reset controller
* @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
* @regset: A pointer to a struct debugfs_regset32, which contains
* a pointer to an array of register definitions, the
* array size and the base address where the register bank
* is to be found.
* @bus_suspended: True if bus is suspended
* @last_frame_num: Number of last frame. Range from 0 to 32768
* @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
* defined, for missed SOFs tracking. Array holds that
* frame numbers, which not equal to last_frame_num +1
* @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
* defined, for missed SOFs tracking.
* If current_frame_number != last_frame_num+1
* then last_frame_num added to this array
* @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
* @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
* 0 - if missed SOFs frame numbers not dumbed
* @fifo_mem: Total internal RAM for FIFOs (bytes)
* @fifo_map: Each bit intend for concrete fifo. If that bit is set,
* then that fifo is used
* @gadget: Represents a usb slave device
* @connected: Used in slave mode. True if device connected with host
* @eps_in: The IN endpoints being supplied to the gadget framework
* @eps_out: The OUT endpoints being supplied to the gadget framework
* @new_connection: Used in host mode. True if there are new connected
* device
* @enabled: Indicates the enabling state of controller
*
*/
struct dwc2_hsotg {
struct device *dev;
......@@ -954,6 +1070,7 @@ struct dwc2_hsotg {
unsigned int gadget_enabled:1;
unsigned int ll_hw_enabled:1;
unsigned int hibernated:1;
u16 frame_number;
struct phy *phy;
struct usb_phy *uphy;
......@@ -1029,7 +1146,6 @@ struct dwc2_hsotg {
u16 periodic_usecs;
unsigned long hs_periodic_bitmap[
DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
u16 frame_number;
u16 periodic_qh_count;
bool bus_suspended;
bool new_connection;
......
drivers/usb/dwc2/core_intr.c
浏览文件 @ 07c4dd34
......@@ -778,6 +778,14 @@ irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
goto out;
}
/* Reading current frame number value in device or host modes. */
if (dwc2_is_device_mode(hsotg))
hsotg->frame_number = (dwc2_readl(hsotg->regs + DSTS)
& DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
else
hsotg->frame_number = (dwc2_readl(hsotg->regs + HFNUM)
& HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
gintsts = dwc2_read_common_intr(hsotg);
if (gintsts & ~GINTSTS_PRTINT)
retval = IRQ_HANDLED;
......
drivers/usb/dwc2/debug.h
浏览文件 @ 07c4dd34
// SPDX-License-Identifier: GPL-2.0
/**
/*
* debug.h - Designware USB2 DRD controller debug header
*
* Copyright (C) 2015 Intel Corporation
......
drivers/usb/dwc2/debugfs.c
浏览文件 @ 07c4dd34
// SPDX-License-Identifier: GPL-2.0
/**
/*
* debugfs.c - Designware USB2 DRD controller debugfs
*
* Copyright (C) 2015 Intel Corporation
......@@ -16,12 +16,13 @@
#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
/**
* testmode_write - debugfs: change usb test mode
* @seq: The seq file to write to.
* @v: Unused parameter.
*
* This debugfs entry modify the current usb test mode.
* testmode_write() - change usb test mode state.
* @file: The file to write to.
* @ubuf: The buffer where user wrote.
* @count: The ubuf size.
* @ppos: Unused parameter.
*/
static ssize_t testmode_write(struct file *file, const char __user *ubuf, size_t
count, loff_t *ppos)
......@@ -55,9 +56,9 @@ static ssize_t testmode_write(struct file *file, const char __user *ubuf, size_t
}
/**
* testmode_show - debugfs: show usb test mode state
* @seq: The seq file to write to.
* @v: Unused parameter.
* testmode_show() - debugfs: show usb test mode state
* @s: The seq file to write to.
* @unused: Unused parameter.
*
* This debugfs entry shows which usb test mode is currently enabled.
*/
......@@ -293,52 +294,30 @@ DEFINE_SHOW_ATTRIBUTE(ep);
static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg)
{
struct dentry *root;
struct dentry *file;
unsigned int epidx;
root = hsotg->debug_root;
/* create general state file */
file = debugfs_create_file("state", 0444, root, hsotg, &state_fops);
if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
file = debugfs_create_file("testmode", 0644, root, hsotg,
&testmode_fops);
if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create testmode\n",
__func__);
file = debugfs_create_file("fifo", 0444, root, hsotg, &fifo_fops);
if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
debugfs_create_file("state", 0444, root, hsotg, &state_fops);
debugfs_create_file("testmode", 0644, root, hsotg, &testmode_fops);
debugfs_create_file("fifo", 0444, root, hsotg, &fifo_fops);
/* Create one file for each out endpoint */
for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
struct dwc2_hsotg_ep *ep;
ep = hsotg->eps_out[epidx];
if (ep) {
file = debugfs_create_file(ep->name, 0444,
root, ep, &ep_fops);
if (IS_ERR(file))
dev_err(hsotg->dev, "failed to create %s debug file\n",
ep->name);
}
if (ep)
debugfs_create_file(ep->name, 0444, root, ep, &ep_fops);
}
/* Create one file for each in endpoint. EP0 is handled with out eps */
for (epidx = 1; epidx < hsotg->num_of_eps; epidx++) {
struct dwc2_hsotg_ep *ep;
ep = hsotg->eps_in[epidx];
if (ep) {
file = debugfs_create_file(ep->name, 0444,
root, ep, &ep_fops);
if (IS_ERR(file))
dev_err(hsotg->dev, "failed to create %s debug file\n",
ep->name);
}
if (ep)
debugfs_create_file(ep->name, 0444, root, ep, &ep_fops);
}
}
#else
......@@ -368,7 +347,7 @@ static const struct debugfs_reg32 dwc2_regs[] = {
dump_register(GINTSTS),
dump_register(GINTMSK),
dump_register(GRXSTSR),
dump_register(GRXSTSP),
/* Omit GRXSTSP */
dump_register(GRXFSIZ),
dump_register(GNPTXFSIZ),
dump_register(GNPTXSTS),
......@@ -710,6 +689,7 @@ static int params_show(struct seq_file *seq, void *v)
print_param(seq, p, phy_ulpi_ddr);
print_param(seq, p, phy_ulpi_ext_vbus);
print_param(seq, p, i2c_enable);
print_param(seq, p, ipg_isoc_en);
print_param(seq, p, ulpi_fs_ls);
print_param(seq, p, host_support_fs_ls_low_power);
print_param(seq, p, host_ls_low_power_phy_clk);
......@@ -790,32 +770,14 @@ DEFINE_SHOW_ATTRIBUTE(dr_mode);
int dwc2_debugfs_init(struct dwc2_hsotg *hsotg)
{
int ret;
struct dentry *file;
struct dentry *root;
hsotg->debug_root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
if (!hsotg->debug_root) {
ret = -ENOMEM;
goto err0;
}
root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
hsotg->debug_root = root;
file = debugfs_create_file("params", 0444,
hsotg->debug_root,
hsotg, &params_fops);
if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create params\n", __func__);
file = debugfs_create_file("hw_params", 0444,
hsotg->debug_root,
hsotg, &hw_params_fops);
if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create hw_params\n",
__func__);
file = debugfs_create_file("dr_mode", 0444,
hsotg->debug_root,
hsotg, &dr_mode_fops);
if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create dr_mode\n", __func__);
debugfs_create_file("params", 0444, root, hsotg, &params_fops);
debugfs_create_file("hw_params", 0444, root, hsotg, &hw_params_fops);
debugfs_create_file("dr_mode", 0444, root, hsotg, &dr_mode_fops);
/* Add gadget debugfs nodes */
dwc2_hsotg_create_debug(hsotg);
......@@ -824,24 +786,18 @@ int dwc2_debugfs_init(struct dwc2_hsotg *hsotg)
GFP_KERNEL);
if (!hsotg->regset) {
ret = -ENOMEM;
goto err1;
goto err;
}
hsotg->regset->regs = dwc2_regs;
hsotg->regset->nregs = ARRAY_SIZE(dwc2_regs);
hsotg->regset->base = hsotg->regs;
file = debugfs_create_regset32("regdump", 0444, hsotg->debug_root,
hsotg->regset);
if (!file) {
ret = -ENOMEM;
goto err1;
}
debugfs_create_regset32("regdump", 0444, root, hsotg->regset);
return 0;
err1:
err:
debugfs_remove_recursive(hsotg->debug_root);
err0:
return ret;
}
......
drivers/usb/dwc2/gadget.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc2/hcd.c
浏览文件 @ 07c4dd34
......@@ -597,7 +597,7 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
* dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
* buffer
*
* @core_if: Programming view of DWC_otg controller
* @hsotg: Programming view of DWC_otg controller
* @dest: Destination buffer for the packet
* @bytes: Number of bytes to copy to the destination
*/
......@@ -4087,7 +4087,6 @@ static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
* then the refcount for the structure will go to 0 and we'll free it.
*
* @hsotg: The HCD state structure for the DWC OTG controller.
* @qh: The QH structure.
* @context: The priv pointer from a struct dwc2_hcd_urb.
* @mem_flags: Flags for allocating memory.
* @ttport: We'll return this device's port number here. That's used to
......
drivers/usb/dwc2/hcd.h
浏览文件 @ 07c4dd34
......@@ -80,7 +80,7 @@ struct dwc2_qh;
* @xfer_count: Number of bytes transferred so far
* @start_pkt_count: Packet count at start of transfer
* @xfer_started: True if the transfer has been started
* @ping: True if a PING request should be issued on this channel
* @do_ping: True if a PING request should be issued on this channel
* @error_state: True if the error count for this transaction is non-zero
* @halt_on_queue: True if this channel should be halted the next time a
* request is queued for the channel. This is necessary in
......@@ -102,7 +102,7 @@ struct dwc2_qh;
* @schinfo: Scheduling micro-frame bitmap
* @ntd: Number of transfer descriptors for the transfer
* @halt_status: Reason for halting the host channel
* @hcint Contents of the HCINT register when the interrupt came
* @hcint: Contents of the HCINT register when the interrupt came
* @qh: QH for the transfer being processed by this channel
* @hc_list_entry: For linking to list of host channels
* @desc_list_addr: Current QH's descriptor list DMA address
......@@ -237,7 +237,7 @@ struct dwc2_tt {
/**
* struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
*
* @start_schedule_usecs: The start time on the main bus schedule. Note that
* @start_schedule_us: The start time on the main bus schedule. Note that
* the main bus schedule is tightly packed and this
* time should be interpreted as tightly packed (so
* uFrame 0 starts at 0 us, uFrame 1 starts at 100 us
......@@ -301,7 +301,6 @@ struct dwc2_hs_transfer_time {
* "struct dwc2_tt". Not used if this device is high
* speed. Note that this is in "schedule slice" which
* is tightly packed.
* @ls_duration_us: Duration on the low speed bus schedule.
* @ntd: Actual number of transfer descriptors in a list
* @qtd_list: List of QTDs for this QH
* @channel: Host channel currently processing transfers for this QH
......@@ -315,7 +314,7 @@ struct dwc2_hs_transfer_time {
* descriptor
* @unreserve_timer: Timer for releasing periodic reservation.
* @wait_timer: Timer used to wait before re-queuing.
* @dwc2_tt: Pointer to our tt info (or NULL if no tt).
* @dwc_tt: Pointer to our tt info (or NULL if no tt).
* @ttport: Port number within our tt.
* @tt_buffer_dirty True if clear_tt_buffer_complete is pending
* @unreserve_pending: True if we planned to unreserve but haven't yet.
......@@ -325,6 +324,7 @@ struct dwc2_hs_transfer_time {
* periodic transfers and is ignored for periodic ones.
* @wait_timer_cancel: Set to true to cancel the wait_timer.
*
* @tt_buffer_dirty: True if EP's TT buffer is not clean.
* A Queue Head (QH) holds the static characteristics of an endpoint and
* maintains a list of transfers (QTDs) for that endpoint. A QH structure may
* be entered in either the non-periodic or periodic schedule.
......@@ -400,6 +400,10 @@ struct dwc2_qh {
* @urb: URB for this transfer
* @qh: Queue head for this QTD
* @qtd_list_entry: For linking to the QH's list of QTDs
* @isoc_td_first: Index of first activated isochronous transfer
* descriptor in Descriptor DMA mode
* @isoc_td_last: Index of last activated isochronous transfer
* descriptor in Descriptor DMA mode
*
* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
* interrupt, or isochronous transfer. A single QTD is created for each URB
......
drivers/usb/dwc2/hcd_ddma.c
浏览文件 @ 07c4dd34
......@@ -332,6 +332,7 @@ static void dwc2_release_channel_ddma(struct dwc2_hsotg *hsotg,
*
* @hsotg: The HCD state structure for the DWC OTG controller
* @qh: The QH to init
* @mem_flags: Indicates the type of memory allocation
*
* Return: 0 if successful, negative error code otherwise
*
......
drivers/usb/dwc2/hcd_intr.c
浏览文件 @ 07c4dd34
......@@ -478,6 +478,12 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
* of the URB based on the number of bytes transferred via the host channel.
* Sets the URB status if the data transfer is finished.
*
* @hsotg: Programming view of the DWC_otg controller
* @chan: Programming view of host channel
* @chnum: Channel number
* @urb: Processing URB
* @qtd: Queue transfer descriptor
*
* Return: 1 if the data transfer specified by the URB is completely finished,
* 0 otherwise
*/
......@@ -566,6 +572,12 @@ void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
* halt_status. Completes the Isochronous URB if all the URB frames have been
* completed.
*
* @hsotg: Programming view of the DWC_otg controller
* @chan: Programming view of host channel
* @chnum: Channel number
* @halt_status: Reason for halting a host channel
* @qtd: Queue transfer descriptor
*
* Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
* transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
*/
......
drivers/usb/dwc2/hcd_queue.c
浏览文件 @ 07c4dd34
......@@ -679,6 +679,7 @@ static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
*
* @hsotg: The HCD state structure for the DWC OTG controller.
* @qh: QH for the periodic transfer.
* @index: Transfer index
*/
static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
struct dwc2_qh *qh, int index)
......@@ -1276,7 +1277,7 @@ static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
* release the reservation. This worker is called after the appropriate
* delay.
*
* @work: Pointer to a qh unreserve_work.
* @t: Address to a qh unreserve_work.
*/
static void dwc2_unreserve_timer_fn(struct timer_list *t)
{
......@@ -1631,7 +1632,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
* @hsotg: The HCD state structure for the DWC OTG controller
* @urb: Holds the information about the device/endpoint needed
* to initialize the QH
* @atomic_alloc: Flag to do atomic allocation if needed
* @mem_flags: Flags for allocating memory.
*
* Return: Pointer to the newly allocated QH, or NULL on error
*/
......
drivers/usb/dwc2/hw.h
浏览文件 @ 07c4dd34
......@@ -311,6 +311,7 @@
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
#define GHWCFG4_ACG_SUPPORTED BIT(12)
#define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11)
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
......@@ -424,6 +425,7 @@
#define DCFG_EPMISCNT_SHIFT 18
#define DCFG_EPMISCNT_LIMIT 0x1f
#define DCFG_EPMISCNT(_x) ((_x) << 18)
#define DCFG_IPG_ISOC_SUPPORDED BIT(17)
#define DCFG_PERFRINT_MASK (0x3 << 11)
#define DCFG_PERFRINT_SHIFT 11
#define DCFG_PERFRINT_LIMIT 0x3
......
drivers/usb/dwc2/params.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc2/pci.c
浏览文件 @ 07c4dd34
......@@ -77,6 +77,12 @@ static int dwc2_pci_quirks(struct pci_dev *pdev, struct platform_device *dwc2)
return 0;
}
/**
* dwc2_pci_probe() - Provides the cleanup entry points for the DWC_otg PCI
* driver
*
* @pci: The programming view of DWC_otg PCI
*/
static void dwc2_pci_remove(struct pci_dev *pci)
{
struct dwc2_pci_glue *glue = pci_get_drvdata(pci);
......
drivers/usb/dwc3/Kconfig
浏览文件 @ 07c4dd34
......@@ -106,4 +106,16 @@ config USB_DWC3_ST
inside (i.e. STiH407).
Say 'Y' or 'M' if you have one such device.
config USB_DWC3_QCOM
tristate "Qualcomm Platform"
depends on ARCH_QCOM || COMPILE_TEST
depends on OF
default USB_DWC3
help
Some Qualcomm SoCs use DesignWare Core IP for USB2/3
functionality.
This driver also handles Qscratch wrapper which is needed
for peripheral mode support.
Say 'Y' or 'M' if you have one such device.
endif
drivers/usb/dwc3/Makefile
浏览文件 @ 07c4dd34
......@@ -48,3 +48,4 @@ obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o
obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o
obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o
obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o
obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o
drivers/usb/dwc3/core.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/core.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/debug.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/debugfs.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/drd.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/dwc3-of-simple.c
浏览文件 @ 07c4dd34
......@@ -208,13 +208,13 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
};
static const struct of_device_id of_dwc3_simple_match[] = {
{ .compatible = "qcom,dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "xlnx,zynqmp-dwc3" },
{ .compatible = "cavium,octeon-7130-usb-uctl" },
{ .compatible = "sprd,sc9860-dwc3" },
{ .compatible = "amlogic,meson-axg-dwc3" },
{ .compatible = "amlogic,meson-gxl-dwc3" },
{ .compatible = "allwinner,sun50i-h6-dwc3" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
......
drivers/usb/dwc3/dwc3-qcom.c 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/ep0.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/gadget.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/gadget.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/dwc3/trace.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/composite.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/function/f_ecm.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/function/f_fs.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/function/rndis.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/Kconfig
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/Makefile
浏览文件 @ 07c4dd34
......@@ -39,4 +39,5 @@ obj-$(CONFIG_USB_MV_U3D) += mv_u3d_core.o
obj-$(CONFIG_USB_GR_UDC) += gr_udc.o
obj-$(CONFIG_USB_GADGET_XILINX) += udc-xilinx.o
obj-$(CONFIG_USB_SNP_UDC_PLAT) += snps_udc_plat.o
obj-$(CONFIG_USB_ASPEED_VHUB) += aspeed-vhub/
obj-$(CONFIG_USB_BDC_UDC) += bdc/
drivers/usb/gadget/udc/aspeed-vhub/Kconfig 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/aspeed-vhub/Makefile 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/aspeed-vhub/core.c 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/aspeed-vhub/dev.c 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/aspeed-vhub/ep0.c 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/aspeed-vhub/epn.c 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/aspeed-vhub/hub.c 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/aspeed-vhub/vhub.h 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/core.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/gr_udc.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/gr_udc.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/pxa27x_udc.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/udc/pxa27x_udc.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/gadget/usbstring.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/Kconfig
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/Makefile
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/ehci-dbg.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/ehci-hcd.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/ehci-omap.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/ehci-tegra.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/fhci-dbg.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/fhci.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/fotg210-hcd.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/imx21-dbg.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/isp116x-hcd.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/ohci-at91.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/ohci-dbg.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/ohci-hcd.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/ohci.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/pci-quirks.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/pci-quirks.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/uhci-hcd.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-dbgcap.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-dbgcap.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-dbgtty.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-debugfs.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-histb.c 0 → 100644
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-hub.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-mem.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-mtk-sch.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-pci.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-ring.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci-tegra.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/host/xhci.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/isp1760/isp1760-core.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/isp1760/isp1760-hcd.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/misc/sisusbvga/sisusb.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mon/mon_bin.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mon/mon_text.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mtu3/Kconfig
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mtu3/mtu3.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mtu3/mtu3_core.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mtu3/mtu3_dr.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mtu3/mtu3_gadget.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mtu3/mtu3_gadget_ep0.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/mtu3/mtu3_plat.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/am35x.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/da8xx.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/davinci.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_core.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_core.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_cppi41.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_debug.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_debugfs.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_dma.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_dsps.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_gadget.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_gadget.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_host.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_io.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_regs.h
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musb_virthub.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musbhsdma.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/musbhsdma.h 已删除 100644 → 0
浏览文件 @ f60342fa
此差异已折叠。
drivers/usb/musb/omap2430.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/sunxi.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/musb/ux500.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/phy/Kconfig
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/phy/Makefile
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/phy/phy-am335x.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/phy/phy-tegra-usb.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/phy/phy.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/renesas_usbhs/common.h
浏览文件 @ 07c4dd34
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drivers/usb/renesas_usbhs/rcar2.c
浏览文件 @ 07c4dd34
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drivers/usb/serial/bus.c
浏览文件 @ 07c4dd34
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drivers/usb/serial/ftdi_sio.c
浏览文件 @ 07c4dd34
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drivers/usb/serial/option.c
浏览文件 @ 07c4dd34
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drivers/usb/serial/pl2303.c
浏览文件 @ 07c4dd34
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drivers/usb/serial/usb-serial.c
浏览文件 @ 07c4dd34
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drivers/usb/storage/freecom.c
浏览文件 @ 07c4dd34
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drivers/usb/storage/uas.c
浏览文件 @ 07c4dd34
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drivers/usb/storage/unusual_devs.h
浏览文件 @ 07c4dd34
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drivers/usb/storage/unusual_uas.h
浏览文件 @ 07c4dd34
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drivers/usb/typec/Kconfig
浏览文件 @ 07c4dd34
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drivers/usb/typec/fusb302/Kconfig
浏览文件 @ 07c4dd34
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drivers/usb/typec/fusb302/fusb302.c
浏览文件 @ 07c4dd34
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drivers/usb/typec/mux.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/typec/tcpm.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/typec/typec_wcove.c
浏览文件 @ 07c4dd34
此差异已折叠。
drivers/usb/usbip/vhci_sysfs.c
浏览文件 @ 07c4dd34
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include/dt-bindings/phy/phy-qcom-qusb2.h 0 → 100644
浏览文件 @ 07c4dd34
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include/linux/power_supply.h
浏览文件 @ 07c4dd34
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include/linux/tty.h
浏览文件 @ 07c4dd34
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include/linux/usb.h
浏览文件 @ 07c4dd34
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include/linux/usb/atmel_usba_udc.h 已删除 100644 → 0
浏览文件 @ f60342fa
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include/linux/usb/audio-v2.h
浏览文件 @ 07c4dd34
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include/linux/usb/gadget.h
浏览文件 @ 07c4dd34
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include/linux/usb/hcd.h
浏览文件 @ 07c4dd34
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include/linux/usb/musb.h
浏览文件 @ 07c4dd34
此差异已折叠。
include/linux/usb/pd.h
浏览文件 @ 07c4dd34
此差异已折叠。
include/linux/usb/phy.h
浏览文件 @ 07c4dd34
此差异已折叠。
include/linux/usb/tcpm.h
浏览文件 @ 07c4dd34
此差异已折叠。
include/linux/usb/tegra_usb_phy.h
浏览文件 @ 07c4dd34
此差异已折叠。
include/uapi/linux/usb/ch11.h
浏览文件 @ 07c4dd34
此差异已折叠。
tools/testing/selftests/drivers/usb/usbip/usbip_test.sh 0 → 100755
浏览文件 @ 07c4dd34
此差异已折叠。
tools/usb/usbip/src/usbip_detach.c
浏览文件 @ 07c4dd34
此差异已折叠。
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