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提交 04bd4638 编写于 作者: S Sujith 提交者： John W. Linville
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ath9k: Use cleaner debug masks 

Remove all the useless __func__ prefixes in debug messages,
and replace the DPRINTF macro with a function.
Signed-off-by: NSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 d9a1f486
展开全部 隐藏空白更改
内联 并排
Showing with 429 addition and 609 deletion
drivers/net/wireless/ath9k/ani.c
浏览文件 @ 04bd4638
...@@ -53,8 +53,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, ...@@ -53,8 +53,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: level out of range (%u > %u)\n", "level out of range (%u > %u)\n",
__func__, level, level,
(unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired));
return false; return false;
} }
...@@ -158,8 +158,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, ...@@ -158,8 +158,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
if (level >= ARRAY_SIZE(firstep)) { if (level >= ARRAY_SIZE(firstep)) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: level out of range (%u > %u)\n", "level out of range (%u > %u)\n",
__func__, level, level,
(unsigned) ARRAY_SIZE(firstep)); (unsigned) ARRAY_SIZE(firstep));
return false; return false;
} }
...@@ -180,8 +180,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, ...@@ -180,8 +180,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
if (level >= ARRAY_SIZE(cycpwrThr1)) { if (level >= ARRAY_SIZE(cycpwrThr1)) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: level out of range (%u > %u)\n", "level out of range (%u > %u)\n",
__func__, level, level,
(unsigned) (unsigned)
ARRAY_SIZE(cycpwrThr1)); ARRAY_SIZE(cycpwrThr1));
return false; return false;
...@@ -200,11 +200,11 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, ...@@ -200,11 +200,11 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: invalid cmd %u\n", __func__, cmd); "invalid cmd %u\n", cmd);
return false; return false;
} }
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "ANI parameters:\n");
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"noiseImmunityLevel=%d, spurImmunityLevel=%d, " "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
"ofdmWeakSigDetectOff=%d\n", "ofdmWeakSigDetectOff=%d\n",
...@@ -262,8 +262,8 @@ static void ath9k_ani_restart(struct ath_hal *ah) ...@@ -262,8 +262,8 @@ static void ath9k_ani_restart(struct ath_hal *ah)
AR_PHY_COUNTMAX - aniState->cckTrigHigh; AR_PHY_COUNTMAX - aniState->cckTrigHigh;
} }
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: Writing ofdmbase=%u cckbase=%u\n", "Writing ofdmbase=%u cckbase=%u\n",
__func__, aniState->ofdmPhyErrBase, aniState->ofdmPhyErrBase,
aniState->cckPhyErrBase); aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
...@@ -490,8 +490,7 @@ void ath9k_ani_reset(struct ath_hal *ah) ...@@ -490,8 +490,7 @@ void ath9k_ani_reset(struct ath_hal *ah)
if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
&& ah->ah_opmode != ATH9K_M_IBSS) { && ah->ah_opmode != ATH9K_M_IBSS) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: Reset ANI state opmode %u\n", __func__, "Reset ANI state opmode %u\n", ah->ah_opmode);
ah->ah_opmode);
ahp->ah_stats.ast_ani_reset++; ahp->ah_stats.ast_ani_reset++;
ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
...@@ -581,9 +580,9 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, ...@@ -581,9 +580,9 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
phyCnt2 < aniState->cckPhyErrBase) { phyCnt2 < aniState->cckPhyErrBase) {
if (phyCnt1 < aniState->ofdmPhyErrBase) { if (phyCnt1 < aniState->ofdmPhyErrBase) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: phyCnt1 0x%x, resetting " "phyCnt1 0x%x, resetting "
"counter value to 0x%x\n", "counter value to 0x%x\n",
__func__, phyCnt1, phyCnt1,
aniState->ofdmPhyErrBase); aniState->ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1, REG_WRITE(ah, AR_PHY_ERR_1,
aniState->ofdmPhyErrBase); aniState->ofdmPhyErrBase);
...@@ -592,9 +591,9 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, ...@@ -592,9 +591,9 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
} }
if (phyCnt2 < aniState->cckPhyErrBase) { if (phyCnt2 < aniState->cckPhyErrBase) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: phyCnt2 0x%x, resetting " "phyCnt2 0x%x, resetting "
"counter value to 0x%x\n", "counter value to 0x%x\n",
__func__, phyCnt2, phyCnt2,
aniState->cckPhyErrBase); aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_2, REG_WRITE(ah, AR_PHY_ERR_2,
aniState->cckPhyErrBase); aniState->cckPhyErrBase);
...@@ -692,8 +691,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, ...@@ -692,8 +691,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
if (cycles == 0 || cycles > cc) { if (cycles == 0 || cycles > cc) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: cycle counter wrap. ExtBusy = 0\n", "cycle counter wrap. ExtBusy = 0\n");
__func__);
good = 0; good = 0;
} else { } else {
u32 cc_d = cc - cycles; u32 cc_d = cc - cycles;
......
drivers/net/wireless/ath9k/beacon.c
浏览文件 @ 04bd4638
...@@ -41,8 +41,7 @@ static int ath_beaconq_config(struct ath_softc *sc) ...@@ -41,8 +41,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) { if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to update h/w beacon queue parameters\n", "unable to update h/w beacon queue parameters\n");
__func__);
return 0; return 0;
} else { } else {
ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
...@@ -53,8 +52,8 @@ static int ath_beaconq_config(struct ath_softc *sc) ...@@ -53,8 +52,8 @@ static int ath_beaconq_config(struct ath_softc *sc)
static void ath_bstuck_process(struct ath_softc *sc) static void ath_bstuck_process(struct ath_softc *sc)
{ {
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: stuck beacon; resetting (bmiss count %u)\n", "stuck beacon; resetting (bmiss count %u)\n",
__func__, sc->sc_bmisscount); sc->sc_bmisscount);
ath_reset(sc, false); ath_reset(sc, false);
} }
...@@ -76,8 +75,7 @@ static void ath_beacon_setup(struct ath_softc *sc, ...@@ -76,8 +75,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
int ctsrate = 0; int ctsrate = 0;
int ctsduration = 0; int ctsduration = 0;
DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n", DPRINTF(sc, ATH_DBG_BEACON, "m %p len %u\n", skb, skb->len);
__func__, skb, skb->len);
/* setup descriptors */ /* setup descriptors */
ds = bf->bf_desc; ds = bf->bf_desc;
...@@ -158,8 +156,8 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) ...@@ -158,8 +156,8 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
cabq = sc->sc_cabq; cabq = sc->sc_cabq;
if (avp->av_bcbuf == NULL) { if (avp->av_bcbuf == NULL) {
DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n",
__func__, avp, avp->av_bcbuf); avp, avp->av_bcbuf);
return NULL; return NULL;
} }
...@@ -216,7 +214,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) ...@@ -216,7 +214,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
if (sc->sc_nvaps > 1) { if (sc->sc_nvaps > 1) {
ath_tx_draintxq(sc, cabq, false); ath_tx_draintxq(sc, cabq, false);
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: flush previous cabq traffic\n", __func__); "flush previous cabq traffic\n");
} }
} }
...@@ -253,8 +251,8 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) ...@@ -253,8 +251,8 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
avp = (void *)vif->drv_priv; avp = (void *)vif->drv_priv;
if (avp->av_bcbuf == NULL) { if (avp->av_bcbuf == NULL) {
DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n",
__func__, avp, avp != NULL ? avp->av_bcbuf : NULL); avp, avp != NULL ? avp->av_bcbuf : NULL);
return; return;
} }
bf = avp->av_bcbuf; bf = avp->av_bcbuf;
...@@ -266,7 +264,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) ...@@ -266,7 +264,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
/* NB: caller is known to have already stopped tx dma */ /* NB: caller is known to have already stopped tx dma */
ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
ath9k_hw_txstart(ah, sc->sc_bhalq); ath9k_hw_txstart(ah, sc->sc_bhalq);
DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__, DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc);
} }
...@@ -351,8 +349,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) ...@@ -351,8 +349,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
*/ */
skb = ieee80211_beacon_get(sc->hw, vif); skb = ieee80211_beacon_get(sc->hw, vif);
if (skb == NULL) { if (skb == NULL) {
DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n", DPRINTF(sc, ATH_DBG_BEACON, "cannot get skb\n");
__func__);
return -ENOMEM; return -ENOMEM;
} }
...@@ -388,8 +385,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) ...@@ -388,8 +385,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */ val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: %s beacons, bslot %d intval %u tsfadjust %llu\n", "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
__func__, "stagger",
avp->av_bslot, intval, (unsigned long long)tsfadjust); avp->av_bslot, intval, (unsigned long long)tsfadjust);
hdr = (struct ieee80211_hdr *)skb->data; hdr = (struct ieee80211_hdr *)skb->data;
...@@ -468,40 +464,39 @@ void ath9k_beacon_tasklet(unsigned long data) ...@@ -468,40 +464,39 @@ void ath9k_beacon_tasklet(unsigned long data)
if (sc->sc_bmisscount < BSTUCK_THRESH) { if (sc->sc_bmisscount < BSTUCK_THRESH) {
if (sc->sc_flags & SC_OP_NO_RESET) { if (sc->sc_flags & SC_OP_NO_RESET) {
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: missed %u consecutive beacons\n", "missed %u consecutive beacons\n",
__func__, sc->sc_bmisscount); sc->sc_bmisscount);
if (show_cycles) { if (show_cycles) {
/* /*
* Display cycle counter stats from HW * Display cycle counter stats from HW
* to aide in debug of stickiness. * to aide in debug of stickiness.
*/ */
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: busy times: rx_clear=%d, " "busy times: rx_clear=%d, "
"rx_frame=%d, tx_frame=%d\n", "rx_frame=%d, tx_frame=%d\n",
__func__, rx_clear, rx_frame, rx_clear, rx_frame,
tx_frame); tx_frame);
} else { } else {
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: unable to obtain " "unable to obtain "
"busy times\n", __func__); "busy times\n");
} }
} else { } else {
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: missed %u consecutive beacons\n", "missed %u consecutive beacons\n",
__func__, sc->sc_bmisscount); sc->sc_bmisscount);
} }
} else if (sc->sc_bmisscount >= BSTUCK_THRESH) { } else if (sc->sc_bmisscount >= BSTUCK_THRESH) {
if (sc->sc_flags & SC_OP_NO_RESET) { if (sc->sc_flags & SC_OP_NO_RESET) {
if (sc->sc_bmisscount == BSTUCK_THRESH) { if (sc->sc_bmisscount == BSTUCK_THRESH) {
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: beacon is officially " "beacon is officially "
"stuck\n", __func__); "stuck\n");
ath9k_hw_dmaRegDump(ah); ath9k_hw_dmaRegDump(ah);
} }
} else { } else {
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: beacon is officially stuck\n", "beacon is officially stuck\n");
__func__);
ath_bstuck_process(sc); ath_bstuck_process(sc);
} }
} }
...@@ -511,12 +506,12 @@ void ath9k_beacon_tasklet(unsigned long data) ...@@ -511,12 +506,12 @@ void ath9k_beacon_tasklet(unsigned long data)
if (sc->sc_bmisscount != 0) { if (sc->sc_bmisscount != 0) {
if (sc->sc_flags & SC_OP_NO_RESET) { if (sc->sc_flags & SC_OP_NO_RESET) {
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: resume beacon xmit after %u misses\n", "resume beacon xmit after %u misses\n",
__func__, sc->sc_bmisscount); sc->sc_bmisscount);
} else { } else {
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: resume beacon xmit after %u misses\n", "resume beacon xmit after %u misses\n",
__func__, sc->sc_bmisscount); sc->sc_bmisscount);
} }
sc->sc_bmisscount = 0; sc->sc_bmisscount = 0;
} }
...@@ -536,8 +531,8 @@ void ath9k_beacon_tasklet(unsigned long data) ...@@ -536,8 +531,8 @@ void ath9k_beacon_tasklet(unsigned long data)
if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF]; if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n", "slot %d [tsf %llu tsftu %u intval %u] if_id %d\n",
__func__, slot, (unsigned long long)tsf, tsftu, slot, (unsigned long long)tsf, tsftu,
intval, if_id); intval, if_id);
bfaddr = 0; bfaddr = 0;
...@@ -580,8 +575,7 @@ void ath9k_beacon_tasklet(unsigned long data) ...@@ -580,8 +575,7 @@ void ath9k_beacon_tasklet(unsigned long data)
*/ */
if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) { if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: beacon queue %u did not stop?\n", "beacon queue %u did not stop?\n", sc->sc_bhalq);
__func__, sc->sc_bhalq);
/* NB: the HAL still stops DMA, so proceed */ /* NB: the HAL still stops DMA, so proceed */
} }
...@@ -658,8 +652,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -658,8 +652,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
else if (intval) /* NB: can be 0 for monitor mode */ else if (intval) /* NB: can be 0 for monitor mode */
nexttbtt = roundup(nexttbtt, intval); nexttbtt = roundup(nexttbtt, intval);
DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", DPRINTF(sc, ATH_DBG_BEACON, "nexttbtt %u intval %u (%u)\n",
__func__, nexttbtt, intval, conf.beacon_interval); nexttbtt, intval, conf.beacon_interval);
/* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */ /* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */
if (sc->sc_ah->ah_opmode == ATH9K_M_STA) { if (sc->sc_ah->ah_opmode == ATH9K_M_STA) {
...@@ -746,7 +740,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -746,7 +740,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
bs.bs_sleepduration = bs.bs_dtimperiod; bs.bs_sleepduration = bs.bs_dtimperiod;
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: tsf %llu " "tsf %llu "
"tsf:tu %u " "tsf:tu %u "
"intval %u " "intval %u "
"nexttbtt %u " "nexttbtt %u "
...@@ -758,7 +752,6 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -758,7 +752,6 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
"maxdur %u " "maxdur %u "
"next %u " "next %u "
"timoffset %u\n", "timoffset %u\n",
__func__,
(unsigned long long)tsf, tsftu, (unsigned long long)tsf, tsftu,
bs.bs_intval, bs.bs_intval,
bs.bs_nexttbtt, bs.bs_nexttbtt,
...@@ -798,8 +791,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -798,8 +791,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
} }
#undef FUDGE #undef FUDGE
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"%s: IBSS nexttbtt %u intval %u (%u)\n", "IBSS nexttbtt %u intval %u (%u)\n",
__func__, nexttbtt, nexttbtt,
intval & ~ATH9K_BEACON_RESET_TSF, intval & ~ATH9K_BEACON_RESET_TSF,
conf.beacon_interval); conf.beacon_interval);
......
drivers/net/wireless/ath9k/calib.c
浏览文件 @ 04bd4638
...@@ -31,11 +31,11 @@ static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 }; ...@@ -31,11 +31,11 @@ static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf) static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
{ {
if (nf > ATH9K_NF_TOO_LOW) { if (nf > ATH9K_NF_TOO_LOW) {
DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: noise floor value detected (%d) is " "noise floor value detected (%d) is "
"lower than what we think is a " "lower than what we think is a "
"reasonable value (%d)\n", "reasonable value (%d)\n",
__func__, nf, ATH9K_NF_TOO_LOW); nf, ATH9K_NF_TOO_LOW);
return false; return false;
} }
return true; return true;
...@@ -116,7 +116,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah, ...@@ -116,7 +116,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"NF calibrated [ctl] [chain 1] is %d\n", nf); "NF calibrated [ctl] [chain 1] is %d\n", nf);
nfarray[1] = nf; nfarray[1] = nf;
...@@ -125,7 +125,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah, ...@@ -125,7 +125,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
AR_PHY_CH2_MINCCA_PWR); AR_PHY_CH2_MINCCA_PWR);
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"NF calibrated [ctl] [chain 2] is %d\n", nf); "NF calibrated [ctl] [chain 2] is %d\n", nf);
nfarray[2] = nf; nfarray[2] = nf;
} }
...@@ -139,7 +139,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah, ...@@ -139,7 +139,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"NF calibrated [ext] [chain 0] is %d\n", nf); "NF calibrated [ext] [chain 0] is %d\n", nf);
nfarray[3] = nf; nfarray[3] = nf;
...@@ -161,7 +161,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah, ...@@ -161,7 +161,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
AR_PHY_CH2_EXT_MINCCA_PWR); AR_PHY_CH2_EXT_MINCCA_PWR);
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"NF calibrated [ext] [chain 2] is %d\n", nf); "NF calibrated [ext] [chain 2] is %d\n", nf);
nfarray[5] = nf; nfarray[5] = nf;
} }
...@@ -187,8 +187,7 @@ static bool getNoiseFloorThresh(struct ath_hal *ah, ...@@ -187,8 +187,7 @@ static bool getNoiseFloorThresh(struct ath_hal *ah,
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel flags 0x%x\n", __func__, "invalid channel flags 0x%x\n", chan->channelFlags);
chan->channelFlags);
return false; return false;
} }
...@@ -206,24 +205,22 @@ static void ath9k_hw_setup_calibration(struct ath_hal *ah, ...@@ -206,24 +205,22 @@ static void ath9k_hw_setup_calibration(struct ath_hal *ah,
case IQ_MISMATCH_CAL: case IQ_MISMATCH_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: starting IQ Mismatch Calibration\n", "starting IQ Mismatch Calibration\n");
__func__);
break; break;
case ADC_GAIN_CAL: case ADC_GAIN_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: starting ADC Gain Calibration\n", __func__); "starting ADC Gain Calibration\n");
break; break;
case ADC_DC_CAL: case ADC_DC_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: starting ADC DC Calibration\n", __func__); "starting ADC DC Calibration\n");
break; break;
case ADC_DC_INIT_CAL: case ADC_DC_INIT_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: starting Init ADC DC Calibration\n", "starting Init ADC DC Calibration\n");
__func__);
break; break;
} }
...@@ -594,16 +591,16 @@ void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan, ...@@ -594,16 +591,16 @@ void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
if (ichan == NULL) { if (ichan == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: invalid channel %u/0x%x; no mapping\n", "invalid channel %u/0x%x; no mapping\n",
__func__, chan->channel, chan->channelFlags); chan->channel, chan->channelFlags);
return; return;
} }
if (currCal->calState != CAL_DONE) { if (currCal->calState != CAL_DONE) {
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: Calibration state incorrect, %d\n", "Calibration state incorrect, %d\n",
__func__, currCal->calState); currCal->calState);
return; return;
} }
...@@ -612,8 +609,8 @@ void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan, ...@@ -612,8 +609,8 @@ void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
return; return;
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: Resetting Cal %d state for channel %u/0x%x\n", "Resetting Cal %d state for channel %u/0x%x\n",
__func__, currCal->calData->calType, chan->channel, currCal->calData->calType, chan->channel,
chan->channelFlags); chan->channelFlags);
ichan->CalValid &= ~currCal->calData->calType; ichan->CalValid &= ~currCal->calData->calType;
...@@ -705,8 +702,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah, ...@@ -705,8 +702,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah,
chan->channelFlags &= (~CHANNEL_CW_INT); chan->channelFlags &= (~CHANNEL_CW_INT);
if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: NF did not complete in calibration window\n", "NF did not complete in calibration window\n");
__func__);
nf = 0; nf = 0;
chan->rawNoiseFloor = nf; chan->rawNoiseFloor = nf;
return chan->rawNoiseFloor; return chan->rawNoiseFloor;
...@@ -716,8 +712,8 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah, ...@@ -716,8 +712,8 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah,
if (getNoiseFloorThresh(ah, chan, &nfThresh) if (getNoiseFloorThresh(ah, chan, &nfThresh)
&& nf > nfThresh) { && nf > nfThresh) {
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: noise floor failed detected; " "noise floor failed detected; "
"detected %d, threshold %d\n", __func__, "detected %d, threshold %d\n",
nf, nfThresh); nf, nfThresh);
chan->channelFlags |= CHANNEL_CW_INT; chan->channelFlags |= CHANNEL_CW_INT;
} }
...@@ -759,9 +755,9 @@ s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) ...@@ -759,9 +755,9 @@ s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
ichan = ath9k_regd_check_channel(ah, chan); ichan = ath9k_regd_check_channel(ah, chan);
if (ichan == NULL) { if (ichan == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: invalid channel %u/0x%x; no mapping\n", "invalid channel %u/0x%x; no mapping\n",
__func__, chan->channel, chan->channelFlags); chan->channel, chan->channelFlags);
return ATH_DEFAULT_NOISE_FLOOR; return ATH_DEFAULT_NOISE_FLOOR;
} }
if (ichan->rawNoiseFloor == 0) { if (ichan->rawNoiseFloor == 0) {
...@@ -788,8 +784,8 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, ...@@ -788,8 +784,8 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
if (ichan == NULL) { if (ichan == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u/0x%x; no mapping\n", "invalid channel %u/0x%x; no mapping\n",
__func__, chan->channel, chan->channelFlags); chan->channel, chan->channelFlags);
return false; return false;
} }
...@@ -834,8 +830,8 @@ bool ath9k_hw_init_cal(struct ath_hal *ah, ...@@ -834,8 +830,8 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: offset calibration failed to complete in 1ms; " "offset calibration failed to complete in 1ms; "
"noisy environment?\n", __func__); "noisy environment?\n");
return false; return false;
} }
...@@ -850,22 +846,19 @@ bool ath9k_hw_init_cal(struct ath_hal *ah, ...@@ -850,22 +846,19 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
INIT_CAL(&ahp->ah_adcGainCalData); INIT_CAL(&ahp->ah_adcGainCalData);
INSERT_CAL(ahp, &ahp->ah_adcGainCalData); INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: enabling ADC Gain Calibration.\n", "enabling ADC Gain Calibration.\n");
__func__);
} }
if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) { if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
INIT_CAL(&ahp->ah_adcDcCalData); INIT_CAL(&ahp->ah_adcDcCalData);
INSERT_CAL(ahp, &ahp->ah_adcDcCalData); INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: enabling ADC DC Calibration.\n", "enabling ADC DC Calibration.\n");
__func__);
} }
if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) { if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
INIT_CAL(&ahp->ah_iqCalData); INIT_CAL(&ahp->ah_iqCalData);
INSERT_CAL(ahp, &ahp->ah_iqCalData); INSERT_CAL(ahp, &ahp->ah_iqCalData);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%s: enabling IQ Calibration.\n", "enabling IQ Calibration.\n");
__func__);
} }
ahp->ah_cal_list_curr = ahp->ah_cal_list; ahp->ah_cal_list_curr = ahp->ah_cal_list;
......
drivers/net/wireless/ath9k/core.h
浏览文件 @ 04bd4638
...@@ -84,52 +84,33 @@ struct ath_node; ...@@ -84,52 +84,33 @@ struct ath_node;
static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
/*************/
/* Debugging */
/*************/
enum ATH_DEBUG { enum ATH_DEBUG {
ATH_DBG_RESET = 0x00000001, ATH_DBG_RESET = 0x00000001,
ATH_DBG_PHY_IO = 0x00000002, ATH_DBG_REG_IO = 0x00000002,
ATH_DBG_REG_IO = 0x00000004, ATH_DBG_QUEUE = 0x00000004,
ATH_DBG_QUEUE = 0x00000008, ATH_DBG_EEPROM = 0x00000008,
ATH_DBG_EEPROM = 0x00000010, ATH_DBG_CALIBRATE = 0x00000010,
ATH_DBG_NF_CAL = 0x00000020, ATH_DBG_CHANNEL = 0x00000020,
ATH_DBG_CALIBRATE = 0x00000040, ATH_DBG_INTERRUPT = 0x00000040,
ATH_DBG_CHANNEL = 0x00000080, ATH_DBG_REGULATORY = 0x00000080,
ATH_DBG_INTERRUPT = 0x00000100, ATH_DBG_ANI = 0x00000100,
ATH_DBG_REGULATORY = 0x00000200, ATH_DBG_POWER_MGMT = 0x00000200,
ATH_DBG_ANI = 0x00000400, ATH_DBG_XMIT = 0x00000400,
ATH_DBG_POWER_MGMT = 0x00000800, ATH_DBG_BEACON = 0x00001000,
ATH_DBG_XMIT = 0x00001000, ATH_DBG_CONFIG = 0x00002000,
ATH_DBG_BEACON = 0x00002000, ATH_DBG_KEYCACHE = 0x00004000,
ATH_DBG_RATE = 0x00004000, ATH_DBG_FATAL = 0x00008000,
ATH_DBG_CONFIG = 0x00008000,
ATH_DBG_KEYCACHE = 0x00010000,
ATH_DBG_AGGR = 0x00020000,
ATH_DBG_FATAL = 0x00040000,
ATH_DBG_ANY = 0xffffffff ATH_DBG_ANY = 0xffffffff
}; };
#define DBG_DEFAULT (ATH_DBG_FATAL) #define DBG_DEFAULT (ATH_DBG_FATAL)
#define DPRINTF(sc, _m, _fmt, ...) do { \
if (sc->sc_debug & (_m)) \
printk(_fmt , ##__VA_ARGS__); \
} while (0)
/***************************/
/* Load-time Configuration */
/***************************/
/* Per-instance load-time (note: NOT run-time) configurations
* for Atheros Device */
struct ath_config { struct ath_config {
u32 ath_aggr_prot; u32 ath_aggr_prot;
u16 txpowlimit; u16 txpowlimit;
u16 txpowlimit_override; u16 txpowlimit_override;
u8 cabqReadytime; /* Cabq Readytime % */ u8 cabqReadytime;
u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */ u8 swBeaconProcess;
}; };
/*************************/ /*************************/
...@@ -160,14 +141,13 @@ enum buffer_type { ...@@ -160,14 +141,13 @@ enum buffer_type {
}; };
struct ath_buf_state { struct ath_buf_state {
int bfs_nframes; /* # frames in aggregate */ int bfs_nframes; /* # frames in aggregate */
u16 bfs_al; /* length of aggregate */ u16 bfs_al; /* length of aggregate */
u16 bfs_frmlen; /* length of frame */ u16 bfs_frmlen; /* length of frame */
int bfs_seqno; /* sequence number */ int bfs_seqno; /* sequence number */
int bfs_tidno; /* tid of this frame */ int bfs_tidno; /* tid of this frame */
int bfs_retries; /* current retries */ int bfs_retries; /* current retries */
u32 bf_type; /* BUF_* (enum buffer_type) */ u32 bf_type; /* BUF_* (enum buffer_type) */
/* key type use to encrypt this frame */
u32 bfs_keyix; u32 bfs_keyix;
enum ath9k_key_type bfs_keytype; enum ath9k_key_type bfs_keytype;
}; };
...@@ -213,13 +193,6 @@ struct ath_buf { ...@@ -213,13 +193,6 @@ struct ath_buf {
dma_addr_t bf_dmacontext; dma_addr_t bf_dmacontext;
}; };
/*
* reset the rx buffer.
* any new fields added to the athbuf and require
* reset need to be added to this macro.
* currently bf_status is the only one requires that
* requires reset.
*/
#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
/* hw processing complete, desc processed by hal */ /* hw processing complete, desc processed by hal */
...@@ -263,11 +236,8 @@ void ath_rx_cleanup(struct ath_softc *sc); ...@@ -263,11 +236,8 @@ void ath_rx_cleanup(struct ath_softc *sc);
int ath_rx_tasklet(struct ath_softc *sc, int flush); int ath_rx_tasklet(struct ath_softc *sc, int flush);
#define ATH_TXBUF 512 #define ATH_TXBUF 512
/* max number of transmit attempts (tries) */
#define ATH_TXMAXTRY 13 #define ATH_TXMAXTRY 13
/* max number of 11n transmit attempts (tries) */
#define ATH_11N_TXMAXTRY 10 #define ATH_11N_TXMAXTRY 10
/* max number of tries for management and control frames */
#define ATH_MGT_TXMAXTRY 4 #define ATH_MGT_TXMAXTRY 4
#define WME_BA_BMP_SIZE 64 #define WME_BA_BMP_SIZE 64
#define WME_MAX_BA WME_BA_BMP_SIZE #define WME_MAX_BA WME_BA_BMP_SIZE
...@@ -279,22 +249,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush); ...@@ -279,22 +249,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush);
WME_AC_VO) WME_AC_VO)
/* Wireless Multimedia Extension Defines */ #define WME_AC_BE 0
#define WME_AC_BE 0 /* best effort */ #define WME_AC_BK 1
#define WME_AC_BK 1 /* background */ #define WME_AC_VI 2
#define WME_AC_VI 2 /* video */ #define WME_AC_VO 3
#define WME_AC_VO 3 /* voice */ #define WME_NUM_AC 4
#define WME_NUM_AC 4
/*
* Data transmit queue state. One of these exists for each
* hardware transmit queue. Packets sent to us from above
* are assigned to queues based on their priority. Not all
* devices support a complete set of hardware transmit queues.
* For those devices the array sc_ac2q will map multiple
* priorities to fewer hardware queues (typically all to one
* hardware queue).
*/
struct ath_txq { struct ath_txq {
u32 axq_qnum; /* hardware q number */ u32 axq_qnum; /* hardware q number */
u32 *axq_link; /* link ptr in last TX desc */ u32 *axq_link; /* link ptr in last TX desc */
...@@ -372,14 +332,15 @@ struct ath_xmit_status { ...@@ -372,14 +332,15 @@ struct ath_xmit_status {
#define ATH_TX_BAR 0x04 #define ATH_TX_BAR 0x04
}; };
/* All RSSI values are noise floor adjusted */
struct ath_tx_stat { struct ath_tx_stat {
int rssi; /* RSSI (noise floor ajusted) */ int rssi;
int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ int rssictl[ATH_MAX_ANTENNA];
int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ int rssiextn[ATH_MAX_ANTENNA];
int rateieee; /* data rate xmitted (IEEE rate code) */ int rateieee;
int rateKbps; /* data rate xmitted (Kbps) */ int rateKbps;
int ratecode; /* phy rate code */ int ratecode;
int flags; /* validity flags */ int flags;
/* if any of ctl,extn chain rssis are valid */ /* if any of ctl,extn chain rssis are valid */
#define ATH_TX_CHAIN_RSSI_VALID 0x01 #define ATH_TX_CHAIN_RSSI_VALID 0x01
/* if extn chain rssis are valid */ /* if extn chain rssis are valid */
...@@ -415,7 +376,7 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb); ...@@ -415,7 +376,7 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
/**********************/ /**********************/
#define ADDBA_EXCHANGE_ATTEMPTS 10 #define ADDBA_EXCHANGE_ATTEMPTS 10
#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */ #define ATH_AGGR_DELIM_SZ 4
#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
/* number of delimiters for encryption padding */ /* number of delimiters for encryption padding */
#define ATH_AGGR_ENCRYPTDELIM 10 #define ATH_AGGR_ENCRYPTDELIM 10
...@@ -466,10 +427,9 @@ struct aggr_rifs_param { ...@@ -466,10 +427,9 @@ struct aggr_rifs_param {
/* Per-node aggregation state */ /* Per-node aggregation state */
struct ath_node_aggr { struct ath_node_aggr {
struct ath_atx tx; /* node transmit state */ struct ath_atx tx;
}; };
/* driver-specific node state */
struct ath_node { struct ath_node {
struct ath_softc *an_sc; struct ath_softc *an_sc;
struct ath_node_aggr an_aggr; struct ath_node_aggr an_aggr;
...@@ -500,12 +460,11 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid ...@@ -500,12 +460,11 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid
#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
/* driver-specific vap state */
struct ath_vap { struct ath_vap {
int av_bslot; /* beacon slot index */ int av_bslot;
enum ath9k_opmode av_opmode; /* VAP operational mode */ enum ath9k_opmode av_opmode;
struct ath_buf *av_bcbuf; /* beacon buffer */ struct ath_buf *av_bcbuf;
struct ath_tx_control av_btxctl; /* txctl information for beacon */ struct ath_tx_control av_btxctl;
}; };
/*******************/ /*******************/
...@@ -518,12 +477,11 @@ struct ath_vap { ...@@ -518,12 +477,11 @@ struct ath_vap {
* number of beacon intervals, the game's up. * number of beacon intervals, the game's up.
*/ */
#define BSTUCK_THRESH (9 * ATH_BCBUF) #define BSTUCK_THRESH (9 * ATH_BCBUF)
#define ATH_BCBUF 4 /* number of beacon buffers */ #define ATH_BCBUF 4
#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */ #define ATH_DEFAULT_BINTVAL 100 /* TU */
#define ATH_DEFAULT_BMISS_LIMIT 10 #define ATH_DEFAULT_BMISS_LIMIT 10
#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
/* beacon configuration */
struct ath_beacon_config { struct ath_beacon_config {
u16 beacon_interval; u16 beacon_interval;
u16 listen_interval; u16 listen_interval;
...@@ -674,18 +632,18 @@ struct ath_softc { ...@@ -674,18 +632,18 @@ struct ath_softc {
u8 sc_tx_chainmask; u8 sc_tx_chainmask;
u8 sc_rx_chainmask; u8 sc_rx_chainmask;
enum ath9k_int sc_imask; enum ath9k_int sc_imask;
enum wireless_mode sc_curmode; /* current phy mode */ enum wireless_mode sc_curmode;
enum PROT_MODE sc_protmode; enum PROT_MODE sc_protmode;
u8 sc_nbcnvaps; /* # of vaps sending beacons */ u8 sc_nbcnvaps;
u16 sc_nvaps; /* # of active virtual ap's */ u16 sc_nvaps;
struct ieee80211_vif *sc_vaps[ATH_BCBUF]; struct ieee80211_vif *sc_vaps[ATH_BCBUF];
u8 sc_mcastantenna; u8 sc_mcastantenna;
u8 sc_defant; /* current default antenna */ u8 sc_defant;
u8 sc_rxotherant; /* rx's on non-default antenna */ u8 sc_rxotherant;
struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */ struct ath9k_node_stats sc_halstats;
enum ath9k_ht_extprotspacing sc_ht_extprotspacing; enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
enum ath9k_ht_macmode tx_chan_width; enum ath9k_ht_macmode tx_chan_width;
...@@ -699,22 +657,22 @@ struct ath_softc { ...@@ -699,22 +657,22 @@ struct ath_softc {
} sc_updateslot; /* slot time update fsm */ } sc_updateslot; /* slot time update fsm */
/* Crypto */ /* Crypto */
u32 sc_keymax; /* size of key cache */ u32 sc_keymax;
DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */ DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
u8 sc_splitmic; /* split TKIP MIC keys */ u8 sc_splitmic; /* split TKIP MIC keys */
/* RX */ /* RX */
struct list_head sc_rxbuf; struct list_head sc_rxbuf;
struct ath_descdma sc_rxdma; struct ath_descdma sc_rxdma;
int sc_rxbufsize; /* rx size based on mtu */ int sc_rxbufsize;
u32 *sc_rxlink; /* link ptr in last RX desc */ u32 *sc_rxlink;
/* TX */ /* TX */
struct list_head sc_txbuf; struct list_head sc_txbuf;
struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES]; struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
struct ath_descdma sc_txdma; struct ath_descdma sc_txdma;
u32 sc_txqsetup; u32 sc_txqsetup;
int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */ int sc_haltype2q[ATH9K_WME_AC_VO+1];
u16 seq_no; /* TX sequence number */ u16 seq_no; /* TX sequence number */
/* Beacon */ /* Beacon */
...@@ -724,13 +682,13 @@ struct ath_softc { ...@@ -724,13 +682,13 @@ struct ath_softc {
struct list_head sc_bbuf; struct list_head sc_bbuf;
u32 sc_bhalq; u32 sc_bhalq;
u32 sc_bmisscount; u32 sc_bmisscount;
u32 ast_be_xmit; /* beacons transmitted */ u32 ast_be_xmit;
u64 bc_tstamp; u64 bc_tstamp;
/* Rate */ /* Rate */
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
u8 sc_protrix; /* protection rate index */ u8 sc_protrix;
/* Channel, Band */ /* Channel, Band */
struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX]; struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
...@@ -755,6 +713,7 @@ struct ath_softc { ...@@ -755,6 +713,7 @@ struct ath_softc {
struct ath_ani sc_ani; struct ath_ani sc_ani;
}; };
void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
int ath_reset(struct ath_softc *sc, bool retry_tx); int ath_reset(struct ath_softc *sc, bool retry_tx);
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
......
drivers/net/wireless/ath9k/eeprom.c
浏览文件 @ 04bd4638
...@@ -116,7 +116,7 @@ static int ath9k_hw_flash_map(struct ath_hal *ah) ...@@ -116,7 +116,7 @@ static int ath9k_hw_flash_map(struct ath_hal *ah)
if (!ahp->ah_cal_mem) { if (!ahp->ah_cal_mem) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: cannot remap eeprom region \n", __func__); "cannot remap eeprom region \n");
return -EIO; return -EIO;
} }
...@@ -149,7 +149,7 @@ static bool ath9k_hw_fill_eeprom(struct ath_hal *ah) ...@@ -149,7 +149,7 @@ static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: Reading from EEPROM, not flash\n", __func__); "Reading from EEPROM, not flash\n");
ar5416_eep_start_loc = 256; ar5416_eep_start_loc = 256;
} }
...@@ -162,8 +162,7 @@ static bool ath9k_hw_fill_eeprom(struct ath_hal *ah) ...@@ -162,8 +162,7 @@ static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
eep_data)) { eep_data)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: Unable to read eeprom region \n", "Unable to read eeprom region \n");
__func__);
return false; return false;
} }
eep_data++; eep_data++;
...@@ -185,12 +184,11 @@ static int ath9k_hw_check_eeprom(struct ath_hal *ah) ...@@ -185,12 +184,11 @@ static int ath9k_hw_check_eeprom(struct ath_hal *ah)
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
&magic)) { &magic)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: Reading Magic # failed\n", __func__); "Reading Magic # failed\n");
return false; return false;
} }
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n", DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Read Magic = 0x%04X\n", magic);
__func__, magic);
if (magic != AR5416_EEPROM_MAGIC) { if (magic != AR5416_EEPROM_MAGIC) {
magic2 = swab16(magic); magic2 = swab16(magic);
...@@ -1205,11 +1203,11 @@ bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, ...@@ -1205,11 +1203,11 @@ bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
((pdadcValues[4 * j + 3] & 0xFF) << 24); ((pdadcValues[4 * j + 3] & 0xFF) << 24);
REG_WRITE(ah, regOffset, reg32); REG_WRITE(ah, regOffset, reg32);
DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"PDADC (%d,%4x): %4.4x %8.8x\n", "PDADC (%d,%4x): %4.4x %8.8x\n",
i, regChainOffset, regOffset, i, regChainOffset, regOffset,
reg32); reg32);
DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"PDADC: Chain %d | PDADC %3d Value %3d | " "PDADC: Chain %d | PDADC %3d Value %3d | "
"PDADC %3d Value %3d | PDADC %3d Value %3d | " "PDADC %3d Value %3d | PDADC %3d Value %3d | "
"PDADC %3d Value %3d |\n", "PDADC %3d Value %3d |\n",
......
drivers/net/wireless/ath9k/hw.c
浏览文件 @ 04bd4638
...@@ -104,9 +104,10 @@ bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val) ...@@ -104,9 +104,10 @@ bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
udelay(AH_TIME_QUANTUM); udelay(AH_TIME_QUANTUM);
} }
DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
"%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
__func__, reg, REG_READ(ah, reg), mask, val); "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
reg, REG_READ(ah, reg), mask, val);
return false; return false;
} }
...@@ -188,8 +189,8 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah, ...@@ -188,8 +189,8 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
} }
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"%s: unknown phy %u (rate ix %u)\n", __func__, "Unknown phy %u (rate ix %u)\n",
rates->info[rateix].phy, rateix); rates->info[rateix].phy, rateix);
txTime = 0; txTime = 0;
break; break;
...@@ -355,9 +356,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah) ...@@ -355,9 +356,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
rdData = REG_READ(ah, addr); rdData = REG_READ(ah, addr);
if (rdData != wrData) { if (rdData != wrData) {
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"%s: address test failed " "address test failed "
"addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
__func__, addr, wrData, rdData); addr, wrData, rdData);
return false; return false;
} }
} }
...@@ -367,9 +368,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah) ...@@ -367,9 +368,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
rdData = REG_READ(ah, addr); rdData = REG_READ(ah, addr);
if (wrData != rdData) { if (wrData != rdData) {
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"%s: address test failed " "address test failed "
"addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
__func__, addr, wrData, rdData); addr, wrData, rdData);
return false; return false;
} }
} }
...@@ -449,8 +450,7 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, ...@@ -449,8 +450,7 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
if (ahp == NULL) { if (ahp == NULL) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: cannot allocate memory for state block\n", "Cannot allocate memory for state block\n");
__func__);
*status = -ENOMEM; *status = -ENOMEM;
return NULL; return NULL;
} }
...@@ -497,8 +497,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah) ...@@ -497,8 +497,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah)
rfStatus = ath9k_hw_init_rf(ah, &ecode); rfStatus = ath9k_hw_init_rf(ah, &ecode);
if (!rfStatus) { if (!rfStatus) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: RF setup failed, status %u\n", __func__, "RF setup failed, status %u\n", ecode);
ecode);
return ecode; return ecode;
} }
...@@ -523,9 +522,9 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah) ...@@ -523,9 +522,9 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: 5G Radio Chip Rev 0x%02X is not " "5G Radio Chip Rev 0x%02X is not "
"supported by this driver\n", "supported by this driver\n",
__func__, ah->ah_analog5GhzRev); ah->ah_analog5GhzRev);
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
...@@ -550,7 +549,7 @@ static int ath9k_hw_init_macaddr(struct ath_hal *ah) ...@@ -550,7 +549,7 @@ static int ath9k_hw_init_macaddr(struct ath_hal *ah)
} }
if (sum == 0 || sum == 0xffff * 3) { if (sum == 0 || sum == 0xffff * 3) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: mac address read failed: %pM\n", __func__, "mac address read failed: %pM\n",
ahp->ah_macaddr); ahp->ah_macaddr);
return -EADDRNOTAVAIL; return -EADDRNOTAVAIL;
} }
...@@ -612,7 +611,7 @@ static int ath9k_hw_post_attach(struct ath_hal *ah) ...@@ -612,7 +611,7 @@ static int ath9k_hw_post_attach(struct ath_hal *ah)
if (!ath9k_hw_chip_test(ah)) { if (!ath9k_hw_chip_test(ah)) {
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"%s: hardware self-test failed\n", __func__); "hardware self-test failed\n");
return -ENODEV; return -ENODEV;
} }
...@@ -658,15 +657,13 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ...@@ -658,15 +657,13 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
ahp->ah_intrMitigation = true; ahp->ah_intrMitigation = true;
if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n", DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
__func__);
ecode = -EIO; ecode = -EIO;
goto bad; goto bad;
} }
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n", DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
__func__);
ecode = -EIO; ecode = -EIO;
goto bad; goto bad;
} }
...@@ -682,17 +679,16 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ...@@ -682,17 +679,16 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
} }
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: serialize_regmode is %d\n", "serialize_regmode is %d\n",
__func__, ah->ah_config.serialize_regmode); ah->ah_config.serialize_regmode);
if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
(ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
(ah->ah_macVersion != AR_SREV_VERSION_9160) && (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
(!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) { (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: Mac Chip Rev 0x%02x.%x is not supported by " "Mac Chip Rev 0x%02x.%x is not supported by "
"this driver\n", __func__, "this driver\n", ah->ah_macVersion, ah->ah_macRev);
ah->ah_macVersion, ah->ah_macRev);
ecode = -EOPNOTSUPP; ecode = -EOPNOTSUPP;
goto bad; goto bad;
} }
...@@ -737,7 +733,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ...@@ -737,7 +733,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
} }
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, "This Mac Chip Rev 0x%02x.%x is \n",
ah->ah_macVersion, ah->ah_macRev); ah->ah_macVersion, ah->ah_macRev);
if (AR_SREV_9280_20_OR_LATER(ah)) { if (AR_SREV_9280_20_OR_LATER(ah)) {
...@@ -874,7 +870,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ...@@ -874,7 +870,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
#endif #endif
if (!ath9k_hw_fill_cap_info(ah)) { if (!ath9k_hw_fill_cap_info(ah)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s:failed ath9k_hw_fill_cap_info\n", __func__); "failed ath9k_hw_fill_cap_info\n");
ecode = -EINVAL; ecode = -EINVAL;
goto bad; goto bad;
} }
...@@ -882,8 +878,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ...@@ -882,8 +878,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
ecode = ath9k_hw_init_macaddr(ah); ecode = ath9k_hw_init_macaddr(ah);
if (ecode != 0) { if (ecode != 0) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: failed initializing mac address\n", "failed initializing mac address\n");
__func__);
goto bad; goto bad;
} }
...@@ -1080,8 +1075,7 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us) ...@@ -1080,8 +1075,7 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
struct ath_hal_5416 *ahp = AH5416(ah); struct ath_hal_5416 *ahp = AH5416(ah);
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n", DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
__func__, us);
ahp->ah_acktimeout = (u32) -1; ahp->ah_acktimeout = (u32) -1;
return false; return false;
} else { } else {
...@@ -1097,8 +1091,7 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us) ...@@ -1097,8 +1091,7 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
struct ath_hal_5416 *ahp = AH5416(ah); struct ath_hal_5416 *ahp = AH5416(ah);
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n", DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
__func__, us);
ahp->ah_ctstimeout = (u32) -1; ahp->ah_ctstimeout = (u32) -1;
return false; return false;
} else { } else {
...@@ -1115,7 +1108,7 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu) ...@@ -1115,7 +1108,7 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
if (tu > 0xFFFF) { if (tu > 0xFFFF) {
DPRINTF(ah->ah_sc, ATH_DBG_XMIT, DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
"%s: bad global tx timeout %u\n", __func__, tu); "bad global tx timeout %u\n", tu);
ahp->ah_globaltxtimeout = (u32) -1; ahp->ah_globaltxtimeout = (u32) -1;
return false; return false;
} else { } else {
...@@ -1129,8 +1122,8 @@ static void ath9k_hw_init_user_settings(struct ath_hal *ah) ...@@ -1129,8 +1122,8 @@ static void ath9k_hw_init_user_settings(struct ath_hal *ah)
{ {
struct ath_hal_5416 *ahp = AH5416(ah); struct ath_hal_5416 *ahp = AH5416(ah);
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n", DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
__func__, ahp->ah_miscMode); ahp->ah_miscMode);
if (ahp->ah_miscMode != 0) if (ahp->ah_miscMode != 0)
REG_WRITE(ah, AR_PCU_MISC, REG_WRITE(ah, AR_PCU_MISC,
...@@ -1176,7 +1169,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, ...@@ -1176,7 +1169,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_ANY, DPRINTF(ah->ah_sc, ATH_DBG_ANY,
"devid=0x%x not supported.\n", devid); "devid=0x%x not supported.\n", devid);
ah = NULL; ah = NULL;
*error = -ENXIO; *error = -ENXIO;
break; break;
...@@ -1355,13 +1348,13 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, ...@@ -1355,13 +1348,13 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
(u32) ah->ah_powerLimit)); (u32) ah->ah_powerLimit));
if (status != 0) { if (status != 0) {
DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
"%s: error init'ing transmit power\n", __func__); "error init'ing transmit power\n");
return -EIO; return -EIO;
} }
if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"%s: ar5416SetRfRegs failed\n", __func__); "ar5416SetRfRegs failed\n");
return -EIO; return -EIO;
} }
...@@ -1533,8 +1526,7 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) ...@@ -1533,8 +1526,7 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
REG_WRITE(ah, (u16) (AR_RTC_RC), 0); REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) { if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: RTC stuck in MAC reset\n", "RTC stuck in MAC reset\n");
__func__);
return false; return false;
} }
...@@ -1561,8 +1553,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) ...@@ -1561,8 +1553,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
AR_RTC_STATUS, AR_RTC_STATUS,
AR_RTC_STATUS_M, AR_RTC_STATUS_M,
AR_RTC_STATUS_ON)) { AR_RTC_STATUS_ON)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n", DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
__func__);
return false; return false;
} }
...@@ -1641,9 +1632,8 @@ static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah, ...@@ -1641,9 +1632,8 @@ static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
{ {
if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) { if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u/0x%x; not marked as " "invalid channel %u/0x%x; not marked as "
"2GHz or 5GHz\n", __func__, chan->channel, "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
chan->channelFlags);
return NULL; return NULL;
} }
...@@ -1652,9 +1642,9 @@ static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah, ...@@ -1652,9 +1642,9 @@ static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
!IS_CHAN_HT20(chan) && !IS_CHAN_HT20(chan) &&
!IS_CHAN_HT40(chan)) { !IS_CHAN_HT40(chan)) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u/0x%x; not marked as " "invalid channel %u/0x%x; not marked as "
"OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n", "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
__func__, chan->channel, chan->channelFlags); chan->channel, chan->channelFlags);
return NULL; return NULL;
} }
...@@ -1670,8 +1660,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah, ...@@ -1670,8 +1660,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
if (ath9k_hw_numtxpending(ah, qnum)) { if (ath9k_hw_numtxpending(ah, qnum)) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
"%s: Transmit frames pending on queue %d\n", "Transmit frames pending on queue %d\n", qnum);
__func__, qnum);
return false; return false;
} }
} }
...@@ -1679,8 +1668,8 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah, ...@@ -1679,8 +1668,8 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
AR_PHY_RFBUS_GRANT_EN)) { AR_PHY_RFBUS_GRANT_EN)) {
DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"%s: Could not kill baseband RX\n", __func__); "Could not kill baseband RX\n");
return false; return false;
} }
...@@ -1689,13 +1678,13 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah, ...@@ -1689,13 +1678,13 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
if (AR_SREV_9280_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) {
if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: failed to set channel\n", __func__); "failed to set channel\n");
return false; return false;
} }
} else { } else {
if (!(ath9k_hw_set_channel(ah, chan))) { if (!(ath9k_hw_set_channel(ah, chan))) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: failed to set channel\n", __func__); "failed to set channel\n");
return false; return false;
} }
} }
...@@ -1707,7 +1696,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah, ...@@ -1707,7 +1696,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
min((u32) MAX_RATE_POWER, min((u32) MAX_RATE_POWER,
(u32) ah->ah_powerLimit)) != 0) { (u32) ah->ah_powerLimit)) != 0) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: error init'ing transmit power\n", __func__); "error init'ing transmit power\n");
return false; return false;
} }
...@@ -2211,8 +2200,8 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, ...@@ -2211,8 +2200,8 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
if (ath9k_hw_check_chan(ah, chan) == NULL) { if (ath9k_hw_check_chan(ah, chan) == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u/0x%x; no mapping\n", "invalid channel %u/0x%x; no mapping\n",
__func__, chan->channel, chan->channelFlags); chan->channel, chan->channelFlags);
ecode = -EINVAL; ecode = -EINVAL;
goto bad; goto bad;
} }
...@@ -2254,8 +2243,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, ...@@ -2254,8 +2243,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
ath9k_hw_mark_phy_inactive(ah); ath9k_hw_mark_phy_inactive(ah);
if (!ath9k_hw_chip_reset(ah, chan)) { if (!ath9k_hw_chip_reset(ah, chan)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n", DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
__func__);
ecode = -EINVAL; ecode = -EINVAL;
goto bad; goto bad;
} }
...@@ -2289,7 +2277,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, ...@@ -2289,7 +2277,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: error setting board options\n", __func__); "error setting board options\n");
ecode = -EIO; ecode = -EIO;
goto bad; goto bad;
} }
...@@ -2379,15 +2367,13 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, ...@@ -2379,15 +2367,13 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
mask = REG_READ(ah, AR_CFG); mask = REG_READ(ah, AR_CFG);
if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s CFG Byte Swap Set 0x%x\n", __func__, "CFG Byte Swap Set 0x%x\n", mask);
mask);
} else { } else {
mask = mask =
INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
REG_WRITE(ah, AR_CFG, mask); REG_WRITE(ah, AR_CFG, mask);
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s Setting CFG 0x%x\n", __func__, "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
REG_READ(ah, AR_CFG));
} }
} else { } else {
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
...@@ -2412,7 +2398,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) ...@@ -2412,7 +2398,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
if (entry >= ah->ah_caps.keycache_size) { if (entry >= ah->ah_caps.keycache_size) {
DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
"%s: entry %u out of range\n", __func__, entry); "entry %u out of range\n", entry);
return false; return false;
} }
...@@ -2449,7 +2435,7 @@ bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) ...@@ -2449,7 +2435,7 @@ bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
if (entry >= ah->ah_caps.keycache_size) { if (entry >= ah->ah_caps.keycache_size) {
DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
"%s: entry %u out of range\n", __func__, entry); "entry %u out of range\n", entry);
return false; return false;
} }
...@@ -2485,7 +2471,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, ...@@ -2485,7 +2471,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
if (entry >= pCap->keycache_size) { if (entry >= pCap->keycache_size) {
DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
"%s: entry %u out of range\n", __func__, entry); "entry %u out of range\n", entry);
return false; return false;
} }
...@@ -2496,8 +2482,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, ...@@ -2496,8 +2482,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
case ATH9K_CIPHER_AES_CCM: case ATH9K_CIPHER_AES_CCM:
if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
"%s: AES-CCM not supported by " "AES-CCM not supported by mac rev 0x%x\n",
"mac rev 0x%x\n", __func__,
ah->ah_macRev); ah->ah_macRev);
return false; return false;
} }
...@@ -2508,16 +2493,14 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, ...@@ -2508,16 +2493,14 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
if (ATH9K_IS_MIC_ENABLED(ah) if (ATH9K_IS_MIC_ENABLED(ah)
&& entry + 64 >= pCap->keycache_size) { && entry + 64 >= pCap->keycache_size) {
DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
"%s: entry %u inappropriate for TKIP\n", "entry %u inappropriate for TKIP\n", entry);
__func__, entry);
return false; return false;
} }
break; break;
case ATH9K_CIPHER_WEP: case ATH9K_CIPHER_WEP:
if (k->kv_len < LEN_WEP40) { if (k->kv_len < LEN_WEP40) {
DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
"%s: WEP key length %u too small\n", "WEP key length %u too small\n", k->kv_len);
__func__, k->kv_len);
return false; return false;
} }
if (k->kv_len <= LEN_WEP40) if (k->kv_len <= LEN_WEP40)
...@@ -2532,8 +2515,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, ...@@ -2532,8 +2515,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
"%s: cipher %u not supported\n", __func__, "cipher %u not supported\n", k->kv_type);
k->kv_type);
return false; return false;
} }
...@@ -2682,8 +2664,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah, ...@@ -2682,8 +2664,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
} }
if (i == 0) { if (i == 0) {
DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
"%s: Failed to wakeup in %uus\n", "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
__func__, POWER_UP_TIME / 20);
return false; return false;
} }
} }
...@@ -2705,7 +2686,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah, ...@@ -2705,7 +2686,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
}; };
int status = true, setChip = true; int status = true, setChip = true;
DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__, DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
modes[ahp->ah_powerMode], modes[mode], modes[ahp->ah_powerMode], modes[mode],
setChip ? "set chip " : ""); setChip ? "set chip " : "");
...@@ -2722,7 +2703,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah, ...@@ -2722,7 +2703,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
"%s: unknown power mode %u\n", __func__, mode); "Unknown power mode %u\n", mode);
return false; return false;
} }
ahp->ah_powerMode = mode; ahp->ah_powerMode = mode;
...@@ -2899,8 +2880,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) ...@@ -2899,8 +2880,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
if (isr & AR_ISR_RXORN) { if (isr & AR_ISR_RXORN) {
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
"%s: receive FIFO overrun interrupt\n", "receive FIFO overrun interrupt\n");
__func__);
} }
if (!AR_SREV_9100(ah)) { if (!AR_SREV_9100(ah)) {
...@@ -2926,27 +2906,23 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) ...@@ -2926,27 +2906,23 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
if (fatal_int) { if (fatal_int) {
if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
DPRINTF(ah->ah_sc, ATH_DBG_ANY, DPRINTF(ah->ah_sc, ATH_DBG_ANY,
"%s: received PCI FATAL interrupt\n", "received PCI FATAL interrupt\n");
__func__);
} }
if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
DPRINTF(ah->ah_sc, ATH_DBG_ANY, DPRINTF(ah->ah_sc, ATH_DBG_ANY,
"%s: received PCI PERR interrupt\n", "received PCI PERR interrupt\n");
__func__);
} }
} }
if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
"%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n", "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
__func__);
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
REG_WRITE(ah, AR_RC, 0); REG_WRITE(ah, AR_RC, 0);
*masked |= ATH9K_INT_FATAL; *masked |= ATH9K_INT_FATAL;
} }
if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
"%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n", "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
__func__);
} }
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
...@@ -2968,12 +2944,10 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) ...@@ -2968,12 +2944,10 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
u32 mask, mask2; u32 mask, mask2;
struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__, DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
omask, ints);
if (omask & ATH9K_INT_GLOBAL) { if (omask & ATH9K_INT_GLOBAL) {
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n", DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
__func__);
REG_WRITE(ah, AR_IER, AR_IER_DISABLE); REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
(void) REG_READ(ah, AR_IER); (void) REG_READ(ah, AR_IER);
if (!AR_SREV_9100(ah)) { if (!AR_SREV_9100(ah)) {
...@@ -3028,8 +3002,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) ...@@ -3028,8 +3002,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
mask2 |= AR_IMR_S2_CST; mask2 |= AR_IMR_S2_CST;
} }
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
mask);
REG_WRITE(ah, AR_IMR, mask); REG_WRITE(ah, AR_IMR, mask);
mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
AR_IMR_S2_DTIM | AR_IMR_S2_DTIM |
...@@ -3049,8 +3022,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) ...@@ -3049,8 +3022,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
} }
if (ints & ATH9K_INT_GLOBAL) { if (ints & ATH9K_INT_GLOBAL) {
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n", DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
__func__);
REG_WRITE(ah, AR_IER, AR_IER_ENABLE); REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
if (!AR_SREV_9100(ah)) { if (!AR_SREV_9100(ah)) {
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
...@@ -3156,14 +3128,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, ...@@ -3156,14 +3128,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
else else
nextTbtt = bs->bs_nexttbtt; nextTbtt = bs->bs_nexttbtt;
DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__, DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
bs->bs_nextdtim); DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__, DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
nextTbtt); DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
beaconintval);
DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
dtimperiod);
REG_WRITE(ah, AR_NEXT_DTIM, REG_WRITE(ah, AR_NEXT_DTIM,
TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
...@@ -3216,8 +3184,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) ...@@ -3216,8 +3184,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
else if (ah->ah_currentRD == 0x41) else if (ah->ah_currentRD == 0x41)
ah->ah_currentRD = 0x43; ah->ah_currentRD = 0x43;
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: regdomain mapped to 0x%x\n", __func__, "regdomain mapped to 0x%x\n", ah->ah_currentRD);
ah->ah_currentRD);
} }
eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
...@@ -3823,8 +3790,7 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah) ...@@ -3823,8 +3790,7 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah)
count++; count++;
if (count > 10) { if (count > 10) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
__func__);
break; break;
} }
udelay(10); udelay(10);
...@@ -3849,8 +3815,7 @@ bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) ...@@ -3849,8 +3815,7 @@ bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
struct ath_hal_5416 *ahp = AH5416(ah); struct ath_hal_5416 *ahp = AH5416(ah);
if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n", DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
__func__, us);
ahp->ah_slottime = (u32) -1; ahp->ah_slottime = (u32) -1;
return false; return false;
} else { } else {
......
drivers/net/wireless/ath9k/mac.c
浏览文件 @ 04bd4638
...@@ -25,10 +25,10 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah, ...@@ -25,10 +25,10 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
struct ath_hal_5416 *ahp = AH5416(ah); struct ath_hal_5416 *ahp = AH5416(ah);
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
"%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
__func__, ahp->ah_txOkInterruptMask, ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask,
ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask, ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask,
ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask); ahp->ah_txUrnInterruptMask);
REG_WRITE(ah, AR_IMR_S0, REG_WRITE(ah, AR_IMR_S0,
SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
...@@ -126,7 +126,7 @@ bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp) ...@@ -126,7 +126,7 @@ bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp)
bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
{ {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
REG_WRITE(ah, AR_Q_TXE, 1 << q); REG_WRITE(ah, AR_Q_TXE, 1 << q);
...@@ -207,9 +207,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) ...@@ -207,9 +207,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
break; break;
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
"%s: TSF have moved while trying to set " "TSF have moved while trying to set "
"quiet time TSF: 0x%08x\n", "quiet time TSF: 0x%08x\n", tsfLow);
__func__, tsfLow);
} }
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
...@@ -222,9 +221,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) ...@@ -222,9 +221,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
while (ath9k_hw_numtxpending(ah, q)) { while (ath9k_hw_numtxpending(ah, q)) {
if ((--wait) == 0) { if ((--wait) == 0) {
DPRINTF(ah->ah_sc, ATH_DBG_XMIT, DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
"%s: Failed to stop Tx DMA in 100 " "Failed to stop Tx DMA in 100 "
"msec after killing last frame\n", "msec after killing last frame\n");
__func__);
break; break;
} }
udelay(100); udelay(100);
...@@ -523,19 +521,17 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, ...@@ -523,19 +521,17 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
__func__, q);
return false; return false;
} }
qi = &ahp->ah_txq[q]; qi = &ahp->ah_txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
__func__);
return false; return false;
} }
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %p\n", qi);
qi->tqi_ver = qinfo->tqi_ver; qi->tqi_ver = qinfo->tqi_ver;
qi->tqi_subtype = qinfo->tqi_subtype; qi->tqi_subtype = qinfo->tqi_subtype;
...@@ -593,15 +589,13 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, ...@@ -593,15 +589,13 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
__func__, q);
return false; return false;
} }
qi = &ahp->ah_txq[q]; qi = &ahp->ah_txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
__func__);
return false; return false;
} }
...@@ -651,22 +645,21 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, ...@@ -651,22 +645,21 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
break; break;
if (q == pCap->total_queues) { if (q == pCap->total_queues) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
"%s: no available tx queue\n", __func__); "no available tx queue\n");
return -1; return -1;
} }
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "bad tx queue type %u\n", type);
__func__, type);
return -1; return -1;
} }
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
qi = &ahp->ah_txq[q]; qi = &ahp->ah_txq[q];
if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
"%s: tx queue %u already active\n", __func__, q); "tx queue %u already active\n", q);
return -1; return -1;
} }
memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
...@@ -697,19 +690,16 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) ...@@ -697,19 +690,16 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
__func__, q);
return false; return false;
} }
qi = &ahp->ah_txq[q]; qi = &ahp->ah_txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
__func__, q);
return false; return false;
} }
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q);
__func__, q);
qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
ahp->ah_txOkInterruptMask &= ~(1 << q); ahp->ah_txOkInterruptMask &= ~(1 << q);
...@@ -731,19 +721,17 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) ...@@ -731,19 +721,17 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
u32 cwMin, chanCwMin, value; u32 cwMin, chanCwMin, value;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
__func__, q);
return false; return false;
} }
qi = &ahp->ah_txq[q]; qi = &ahp->ah_txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
__func__, q);
return true; return true;
} }
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "reset queue %u\n", q);
if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
if (chan && IS_CHAN_B(chan)) if (chan && IS_CHAN_B(chan))
...@@ -976,8 +964,7 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) ...@@ -976,8 +964,7 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
reg = REG_READ(ah, AR_OBS_BUS_1); reg = REG_READ(ah, AR_OBS_BUS_1);
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"%s: rx failed to go idle in 10 ms RXSM=0x%x\n", "rx failed to go idle in 10 ms RXSM=0x%x\n", reg);
__func__, reg);
return false; return false;
} }
...@@ -1022,9 +1009,8 @@ bool ath9k_hw_stopdmarecv(struct ath_hal *ah) ...@@ -1022,9 +1009,8 @@ bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) { if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
"%s: dma failed to stop in 10ms\n" "dma failed to stop in 10ms\n"
"AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
__func__,
REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
return false; return false;
} else { } else {
......
drivers/net/wireless/ath9k/main.c
浏览文件 @ 04bd4638
此差异已折叠。
drivers/net/wireless/ath9k/phy.c
浏览文件 @ 04bd4638
...@@ -52,8 +52,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) ...@@ -52,8 +52,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
bModeSynth = 1; bModeSynth = 1;
} else { } else {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u MHz\n", __func__, "Invalid channel %u MHz\n", freq);
freq);
return false; return false;
} }
...@@ -86,7 +85,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) ...@@ -86,7 +85,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
aModeRefSel = ath9k_hw_reverse_bits(1, 2); aModeRefSel = ath9k_hw_reverse_bits(1, 2);
} else { } else {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u MHz\n", __func__, freq); "Invalid channel %u MHz\n", freq);
return false; return false;
} }
...@@ -348,8 +347,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) ...@@ -348,8 +347,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
|| ahp->ah_analogBank6TPCData == NULL || ahp->ah_analogBank6TPCData == NULL
|| ahp->ah_analogBank7Data == NULL) { || ahp->ah_analogBank7Data == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"%s: cannot allocate RF banks\n", "Cannot allocate RF banks\n");
__func__);
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
} }
...@@ -360,8 +358,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) ...@@ -360,8 +358,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
ahp->ah_iniAddac.ia_columns), GFP_KERNEL); ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
if (ahp->ah_addac5416_21 == NULL) { if (ahp->ah_addac5416_21 == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"%s: cannot allocate ah_addac5416_21\n", "Cannot allocate ah_addac5416_21\n");
__func__);
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
} }
...@@ -371,8 +368,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) ...@@ -371,8 +368,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
ahp->ah_iniBank6.ia_rows), GFP_KERNEL); ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
if (ahp->ah_bank6Temp == NULL) { if (ahp->ah_bank6Temp == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"%s: cannot allocate ah_bank6Temp\n", "Cannot allocate ah_bank6Temp\n");
__func__);
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
} }
......
drivers/net/wireless/ath9k/rc.c
浏览文件 @ 04bd4638
...@@ -1326,13 +1326,13 @@ static struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc, ...@@ -1326,13 +1326,13 @@ static struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
mode = ATH9K_MODE_11NA_HT40PLUS; mode = ATH9K_MODE_11NA_HT40PLUS;
break; break;
default: default:
DPRINTF(sc, ATH_DBG_RATE, "Invalid band\n"); DPRINTF(sc, ATH_DBG_CONFIG, "Invalid band\n");
return NULL; return NULL;
} }
BUG_ON(mode >= ATH9K_MODE_MAX); BUG_ON(mode >= ATH9K_MODE_MAX);
DPRINTF(sc, ATH_DBG_RATE, "Choosing rate table for mode: %d\n", mode); DPRINTF(sc, ATH_DBG_CONFIG, "Choosing rate table for mode: %d\n", mode);
return sc->hw_rate_table[mode]; return sc->hw_rate_table[mode];
} }
...@@ -1572,8 +1572,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp ...@@ -1572,8 +1572,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp); rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
if (!rate_priv) { if (!rate_priv) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to allocate private rc structure\n", "Unable to allocate private rc structure\n");
__func__);
return NULL; return NULL;
} }
......
drivers/net/wireless/ath9k/recv.c
浏览文件 @ 04bd4638
...@@ -105,8 +105,7 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len) ...@@ -105,8 +105,7 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len)
skb_reserve(skb, sc->sc_cachelsz - off); skb_reserve(skb, sc->sc_cachelsz - off);
} else { } else {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: skbuff alloc of size %u failed\n", "skbuff alloc of size %u failed\n", len);
__func__, len);
return NULL; return NULL;
} }
...@@ -263,11 +262,7 @@ static void ath_opmode_init(struct ath_softc *sc) ...@@ -263,11 +262,7 @@ static void ath_opmode_init(struct ath_softc *sc)
/* calculate and install multicast filter */ /* calculate and install multicast filter */
mfilt[0] = mfilt[1] = ~0; mfilt[0] = mfilt[1] = ~0;
ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
DPRINTF(sc, ATH_DBG_CONFIG ,
"%s: RX filter 0x%x, MC filter %08x:%08x\n",
__func__, rfilt, mfilt[0], mfilt[1]);
} }
int ath_rx_init(struct ath_softc *sc, int nbufs) int ath_rx_init(struct ath_softc *sc, int nbufs)
...@@ -285,8 +280,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) ...@@ -285,8 +280,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
min(sc->sc_cachelsz, min(sc->sc_cachelsz,
(u16)64)); (u16)64));
DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n", DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
__func__, sc->sc_cachelsz, sc->sc_rxbufsize); sc->sc_cachelsz, sc->sc_rxbufsize);
/* Initialize rx descriptors */ /* Initialize rx descriptors */
...@@ -294,8 +289,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) ...@@ -294,8 +289,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
"rx", nbufs, 1); "rx", nbufs, 1);
if (error != 0) { if (error != 0) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: failed to allocate rx descriptors: %d\n", "failed to allocate rx descriptors: %d\n", error);
__func__, error);
break; break;
} }
......
drivers/net/wireless/ath9k/regd.c
浏览文件 @ 04bd4638
...@@ -78,8 +78,7 @@ static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah) ...@@ -78,8 +78,7 @@ static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
return true; return true;
} }
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: invalid regulatory domain/country code 0x%x\n", "invalid regulatory domain/country code 0x%x\n", rd);
__func__, rd);
return false; return false;
} }
...@@ -107,13 +106,12 @@ static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah, ...@@ -107,13 +106,12 @@ static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
return true; return true;
rd = ath9k_regd_get_eepromRD(ah); rd = ath9k_regd_get_eepromRD(ah);
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: EEPROM regdomain 0x%x\n", DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "EEPROM regdomain 0x%x\n", rd);
__func__, rd);
if (rd & COUNTRY_ERD_FLAG) { if (rd & COUNTRY_ERD_FLAG) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: EEPROM setting is country code %u\n", "EEPROM setting is country code %u\n",
__func__, rd & ~COUNTRY_ERD_FLAG); rd & ~COUNTRY_ERD_FLAG);
return cc == (rd & ~COUNTRY_ERD_FLAG); return cc == (rd & ~COUNTRY_ERD_FLAG);
} }
...@@ -290,8 +288,7 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn, ...@@ -290,8 +288,7 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
} }
if (!found) { if (!found) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: Failed to find reg domain pair %u\n", "Failed to find reg domain pair %u\n", regDmn);
__func__, regDmn);
return false; return false;
} }
if (!(channelFlag & CHANNEL_2GHZ)) { if (!(channelFlag & CHANNEL_2GHZ)) {
...@@ -307,8 +304,7 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn, ...@@ -307,8 +304,7 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
found = ath9k_regd_is_valid_reg_domain(regDmn, rd); found = ath9k_regd_is_valid_reg_domain(regDmn, rd);
if (!found) { if (!found) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: Failed to find unitary reg domain %u\n", "Failed to find unitary reg domain %u\n", regDmn);
__func__, regDmn);
return false; return false;
} else { } else {
rd->pscan &= regPair->pscanMask; rd->pscan &= regPair->pscanMask;
...@@ -430,30 +426,27 @@ ath9k_regd_add_channel(struct ath_hal *ah, ...@@ -430,30 +426,27 @@ ath9k_regd_add_channel(struct ath_hal *ah,
if (!(c_lo <= c && c <= c_hi)) { if (!(c_lo <= c && c <= c_hi)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: c %u out of range [%u..%u]\n", "c %u out of range [%u..%u]\n",
__func__, c, c_lo, c_hi); c, c_lo, c_hi);
return false; return false;
} }
if ((fband->channelBW == CHANNEL_HALF_BW) && if ((fband->channelBW == CHANNEL_HALF_BW) &&
!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) { !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: Skipping %u half rate channel\n", "Skipping %u half rate channel\n", c);
__func__, c);
return false; return false;
} }
if ((fband->channelBW == CHANNEL_QUARTER_BW) && if ((fband->channelBW == CHANNEL_QUARTER_BW) &&
!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_QUARTERRATE)) { !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_QUARTERRATE)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: Skipping %u quarter rate channel\n", "Skipping %u quarter rate channel\n", c);
__func__, c);
return false; return false;
} }
if (((c + fband->channelSep) / 2) > (maxChan + HALF_MAXCHANBW)) { if (((c + fband->channelSep) / 2) > (maxChan + HALF_MAXCHANBW)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: c %u > maxChan %u\n", "c %u > maxChan %u\n", c, maxChan);
__func__, c, maxChan);
return false; return false;
} }
...@@ -606,8 +599,7 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah, ...@@ -606,8 +599,7 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah,
} }
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: Skipping %d freq band\n", "Skipping %d freq band\n", j_bandcheck[i].freqbandbit);
__func__, j_bandcheck[i].freqbandbit);
return skipband; return skipband;
} }
...@@ -632,20 +624,19 @@ ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -632,20 +624,19 @@ ath9k_regd_init_channels(struct ath_hal *ah,
unsigned long *modes_avail; unsigned long *modes_avail;
DECLARE_BITMAP(modes_allowed, ATH9K_MODE_MAX); DECLARE_BITMAP(modes_allowed, ATH9K_MODE_MAX);
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: cc %u %s %s\n", DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "cc %u %s %s\n", cc,
__func__, cc,
enableOutdoor ? "Enable outdoor" : "", enableOutdoor ? "Enable outdoor" : "",
enableExtendedChannels ? "Enable ecm" : ""); enableExtendedChannels ? "Enable ecm" : "");
if (!ath9k_regd_is_ccode_valid(ah, cc)) { if (!ath9k_regd_is_ccode_valid(ah, cc)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: invalid country code %d\n", __func__, cc); "Invalid country code %d\n", cc);
return false; return false;
} }
if (!ath9k_regd_is_eeprom_valid(ah)) { if (!ath9k_regd_is_eeprom_valid(ah)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: invalid EEPROM contents\n", __func__); "Invalid EEPROM contents\n");
return false; return false;
} }
...@@ -693,9 +684,9 @@ ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -693,9 +684,9 @@ ath9k_regd_init_channels(struct ath_hal *ah,
~CHANNEL_2GHZ, ~CHANNEL_2GHZ,
&rd5GHz)) { &rd5GHz)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: couldn't find unitary " "Couldn't find unitary "
"5GHz reg domain for country %u\n", "5GHz reg domain for country %u\n",
__func__, ah->ah_countryCode); ah->ah_countryCode);
return false; return false;
} }
if (!ath9k_regd_get_wmode_regdomain(ah, if (!ath9k_regd_get_wmode_regdomain(ah,
...@@ -703,9 +694,9 @@ ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -703,9 +694,9 @@ ath9k_regd_init_channels(struct ath_hal *ah,
CHANNEL_2GHZ, CHANNEL_2GHZ,
&rd2GHz)) { &rd2GHz)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: couldn't find unitary 2GHz " "Couldn't find unitary 2GHz "
"reg domain for country %u\n", "reg domain for country %u\n",
__func__, ah->ah_countryCode); ah->ah_countryCode);
return false; return false;
} }
...@@ -717,9 +708,9 @@ ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -717,9 +708,9 @@ ath9k_regd_init_channels(struct ath_hal *ah,
~CHANNEL_2GHZ, ~CHANNEL_2GHZ,
&rd5GHz)) { &rd5GHz)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: couldn't find unitary 5GHz " "Couldn't find unitary 5GHz "
"reg domain for country %u\n", "reg domain for country %u\n",
__func__, ah->ah_countryCode); ah->ah_countryCode);
return false; return false;
} }
} }
...@@ -749,15 +740,14 @@ ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -749,15 +740,14 @@ ath9k_regd_init_channels(struct ath_hal *ah,
if (!test_bit(cm->mode, modes_avail)) { if (!test_bit(cm->mode, modes_avail)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: !avail mode %d flags 0x%x\n", "!avail mode %d flags 0x%x\n",
__func__, cm->mode, cm->flags); cm->mode, cm->flags);
continue; continue;
} }
if (!ath9k_get_channel_edges(ah, cm->flags, &c_lo, &c_hi)) { if (!ath9k_get_channel_edges(ah, cm->flags, &c_lo, &c_hi)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: channels 0x%x not supported " "channels 0x%x not supported "
"by hardware\n", "by hardware\n", cm->flags);
__func__, cm->flags);
continue; continue;
} }
...@@ -788,8 +778,7 @@ ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -788,8 +778,7 @@ ath9k_regd_init_channels(struct ath_hal *ah,
break; break;
default: default:
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: Unknown HAL mode 0x%x\n", __func__, "Unknown HAL mode 0x%x\n", cm->mode);
cm->mode);
continue; continue;
} }
...@@ -841,9 +830,8 @@ ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -841,9 +830,8 @@ ath9k_regd_init_channels(struct ath_hal *ah,
if (next >= maxchans) { if (next >= maxchans) {
DPRINTF(ah->ah_sc, DPRINTF(ah->ah_sc,
ATH_DBG_REGULATORY, ATH_DBG_REGULATORY,
"%s: too many channels " "too many channels "
"for channel table\n", "for channel table\n");
__func__);
goto done; goto done;
} }
if (ath9k_regd_add_channel(ah, if (ath9k_regd_add_channel(ah,
...@@ -869,9 +857,8 @@ ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -869,9 +857,8 @@ ath9k_regd_init_channels(struct ath_hal *ah,
if (next > ARRAY_SIZE(ah->ah_channels)) { if (next > ARRAY_SIZE(ah->ah_channels)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: too many channels %u; truncating to %u\n", "too many channels %u; truncating to %u\n",
__func__, next, next, (int) ARRAY_SIZE(ah->ah_channels));
(int) ARRAY_SIZE(ah->ah_channels));
next = ARRAY_SIZE(ah->ah_channels); next = ARRAY_SIZE(ah->ah_channels);
} }
#ifdef ATH_NF_PER_CHAN #ifdef ATH_NF_PER_CHAN
...@@ -919,7 +906,7 @@ ath9k_regd_check_channel(struct ath_hal *ah, ...@@ -919,7 +906,7 @@ ath9k_regd_check_channel(struct ath_hal *ah,
int n, lim; int n, lim;
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: channel %u/0x%x (0x%x) requested\n", __func__, "channel %u/0x%x (0x%x) requested\n",
c->channel, c->channelFlags, flags); c->channel, c->channelFlags, flags);
cc = ah->ah_curchan; cc = ah->ah_curchan;
...@@ -950,15 +937,15 @@ ath9k_regd_check_channel(struct ath_hal *ah, ...@@ -950,15 +937,15 @@ ath9k_regd_check_channel(struct ath_hal *ah,
d = flags - (cc->channelFlags & CHAN_FLAGS); d = flags - (cc->channelFlags & CHAN_FLAGS);
} }
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: channel %u/0x%x d %d\n", __func__, "channel %u/0x%x d %d\n",
cc->channel, cc->channelFlags, d); cc->channel, cc->channelFlags, d);
if (d > 0) { if (d > 0) {
base = cc + 1; base = cc + 1;
lim--; lim--;
} }
} }
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: no match for %u/0x%x\n", DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "no match for %u/0x%x\n",
__func__, c->channel, c->channelFlags); c->channel, c->channelFlags);
return NULL; return NULL;
} }
......
drivers/net/wireless/ath9k/xmit.c
浏览文件 @ 04bd4638
...@@ -83,18 +83,16 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, ...@@ -83,18 +83,16 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
DPRINTF(sc, ATH_DBG_QUEUE, DPRINTF(sc, ATH_DBG_QUEUE,
"%s: txq depth = %d\n", __func__, txq->axq_depth); "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
if (txq->axq_link == NULL) { if (txq->axq_link == NULL) {
ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
DPRINTF(sc, ATH_DBG_XMIT, DPRINTF(sc, ATH_DBG_XMIT,
"%s: TXDP[%u] = %llx (%p)\n", "TXDP[%u] = %llx (%p)\n",
__func__, txq->axq_qnum, txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
ito64(bf->bf_daddr), bf->bf_desc);
} else { } else {
*txq->axq_link = bf->bf_daddr; *txq->axq_link = bf->bf_daddr;
DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n", DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
__func__,
txq->axq_qnum, txq->axq_link, txq->axq_qnum, txq->axq_link,
ito64(bf->bf_daddr), bf->bf_desc); ito64(bf->bf_daddr), bf->bf_desc);
} }
...@@ -109,8 +107,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, ...@@ -109,8 +107,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
DPRINTF(sc, ATH_DBG_XMIT, DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
"%s: TX complete: skb: %p\n", __func__, skb);
if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
...@@ -983,8 +980,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) ...@@ -983,8 +980,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
int txok, nbad = 0; int txok, nbad = 0;
int status; int status;
DPRINTF(sc, ATH_DBG_QUEUE, DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
"%s: tx queue %d (%x), link %p\n", __func__,
txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
txq->axq_link); txq->axq_link);
...@@ -1116,9 +1112,9 @@ static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) ...@@ -1116,9 +1112,9 @@ static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
struct ath_hal *ah = sc->sc_ah; struct ath_hal *ah = sc->sc_ah;
(void) ath9k_hw_stoptxdma(ah, txq->axq_qnum); (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n", DPRINTF(sc, ATH_DBG_XMIT, "tx queue [%u] %x, link %p\n",
__func__, txq->axq_qnum, txq->axq_qnum, ath9k_hw_gettxbuf(ah, txq->axq_qnum),
ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link); txq->axq_link);
} }
/* Drain only the data queues */ /* Drain only the data queues */
...@@ -1142,8 +1138,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx) ...@@ -1142,8 +1138,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
if (npend) { if (npend) {
/* TxDMA not stopped, reset the hal */ /* TxDMA not stopped, reset the hal */
DPRINTF(sc, ATH_DBG_XMIT, DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
"%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
spin_lock_bh(&sc->sc_resetlock); spin_lock_bh(&sc->sc_resetlock);
if (!ath9k_hw_reset(ah, if (!ath9k_hw_reset(ah,
...@@ -1153,8 +1148,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx) ...@@ -1153,8 +1148,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
sc->sc_ht_extprotspacing, true, &status)) { sc->sc_ht_extprotspacing, true, &status)) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to reset hardware; hal status %u\n", "Unable to reset hardware; hal status %u\n",
__func__,
status); status);
} }
spin_unlock_bh(&sc->sc_resetlock); spin_unlock_bh(&sc->sc_resetlock);
...@@ -1194,7 +1188,6 @@ static void ath_tx_addto_baw(struct ath_softc *sc, ...@@ -1194,7 +1188,6 @@ static void ath_tx_addto_baw(struct ath_softc *sc,
* Function to send an A-MPDU * Function to send an A-MPDU
* NB: must be called with txq lock held * NB: must be called with txq lock held
*/ */
static int ath_tx_send_ampdu(struct ath_softc *sc, static int ath_tx_send_ampdu(struct ath_softc *sc,
struct ath_atx_tid *tid, struct ath_atx_tid *tid,
struct list_head *bf_head, struct list_head *bf_head,
...@@ -1242,7 +1235,6 @@ static int ath_tx_send_ampdu(struct ath_softc *sc, ...@@ -1242,7 +1235,6 @@ static int ath_tx_send_ampdu(struct ath_softc *sc,
* looks up the rate * looks up the rate
* returns aggr limit based on lowest of the rates * returns aggr limit based on lowest of the rates
*/ */
static u32 ath_lookup_rate(struct ath_softc *sc, static u32 ath_lookup_rate(struct ath_softc *sc,
struct ath_buf *bf, struct ath_buf *bf,
struct ath_atx_tid *tid) struct ath_atx_tid *tid)
...@@ -1310,7 +1302,6 @@ static u32 ath_lookup_rate(struct ath_softc *sc, ...@@ -1310,7 +1302,6 @@ static u32 ath_lookup_rate(struct ath_softc *sc,
* meet the minimum required mpdudensity. * meet the minimum required mpdudensity.
* caller should make sure that the rate is HT rate . * caller should make sure that the rate is HT rate .
*/ */
static int ath_compute_num_delims(struct ath_softc *sc, static int ath_compute_num_delims(struct ath_softc *sc,
struct ath_atx_tid *tid, struct ath_atx_tid *tid,
struct ath_buf *bf, struct ath_buf *bf,
...@@ -1382,7 +1373,6 @@ static int ath_compute_num_delims(struct ath_softc *sc, ...@@ -1382,7 +1373,6 @@ static int ath_compute_num_delims(struct ath_softc *sc,
* For aggregation from software buffer queue. * For aggregation from software buffer queue.
* NB: must be called with txq lock held * NB: must be called with txq lock held
*/ */
static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
struct ath_atx_tid *tid, struct ath_atx_tid *tid,
struct list_head *bf_q, struct list_head *bf_q,
...@@ -1505,7 +1495,6 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, ...@@ -1505,7 +1495,6 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
* process pending frames possibly doing a-mpdu aggregation * process pending frames possibly doing a-mpdu aggregation
* NB: must be called with txq lock held * NB: must be called with txq lock held
*/ */
static void ath_tx_sched_aggr(struct ath_softc *sc, static void ath_tx_sched_aggr(struct ath_softc *sc,
struct ath_txq *txq, struct ath_atx_tid *tid) struct ath_txq *txq, struct ath_atx_tid *tid)
{ {
...@@ -1635,7 +1624,6 @@ static void ath_tid_drain(struct ath_softc *sc, ...@@ -1635,7 +1624,6 @@ static void ath_tid_drain(struct ath_softc *sc,
* Drain all pending buffers * Drain all pending buffers
* NB: must be called with txq lock held * NB: must be called with txq lock held
*/ */
static void ath_txq_drain_pending_buffers(struct ath_softc *sc, static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
struct ath_txq *txq) struct ath_txq *txq)
{ {
...@@ -1795,8 +1783,7 @@ int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb, ...@@ -1795,8 +1783,7 @@ int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
bf = ath_tx_get_buffer(sc); bf = ath_tx_get_buffer(sc);
if (!bf) { if (!bf) {
DPRINTF(sc, ATH_DBG_XMIT, "%s: TX buffers are full\n", DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
__func__);
return -1; return -1;
} }
...@@ -1820,8 +1807,8 @@ int ath_tx_init(struct ath_softc *sc, int nbufs) ...@@ -1820,8 +1807,8 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
"tx", nbufs, 1); "tx", nbufs, 1);
if (error != 0) { if (error != 0) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: failed to allocate tx descriptors: %d\n", "Failed to allocate tx descriptors: %d\n",
__func__, error); error);
break; break;
} }
...@@ -1830,9 +1817,8 @@ int ath_tx_init(struct ath_softc *sc, int nbufs) ...@@ -1830,9 +1817,8 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
"beacon", ATH_BCBUF, 1); "beacon", ATH_BCBUF, 1);
if (error != 0) { if (error != 0) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: failed to allocate " "Failed to allocate beacon descriptors: %d\n",
"beacon descripotrs: %d\n", error);
__func__, error);
break; break;
} }
...@@ -1904,8 +1890,8 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) ...@@ -1904,8 +1890,8 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
} }
if (qnum >= ARRAY_SIZE(sc->sc_txq)) { if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: hal qnum %u out of range, max %u!\n", "qnum %u out of range, max %u!\n",
__func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq)); qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
ath9k_hw_releasetxqueue(ah, qnum); ath9k_hw_releasetxqueue(ah, qnum);
return NULL; return NULL;
} }
...@@ -1950,8 +1936,8 @@ int ath_tx_setup(struct ath_softc *sc, int haltype) ...@@ -1950,8 +1936,8 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: HAL AC %u out of range, max %zu!\n", "HAL AC %u out of range, max %zu!\n",
__func__, haltype, ARRAY_SIZE(sc->sc_haltype2q)); haltype, ARRAY_SIZE(sc->sc_haltype2q));
return 0; return 0;
} }
txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
...@@ -1970,8 +1956,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) ...@@ -1970,8 +1956,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
case ATH9K_TX_QUEUE_DATA: case ATH9K_TX_QUEUE_DATA:
if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: HAL AC %u out of range, max %zu!\n", "HAL AC %u out of range, max %zu!\n",
__func__,
haltype, ARRAY_SIZE(sc->sc_haltype2q)); haltype, ARRAY_SIZE(sc->sc_haltype2q));
return -1; return -1;
} }
...@@ -2004,8 +1989,8 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) ...@@ -2004,8 +1989,8 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
/* Try to avoid running out of descriptors */ /* Try to avoid running out of descriptors */
if (txq->axq_depth >= (ATH_TXBUF - 20)) { if (txq->axq_depth >= (ATH_TXBUF - 20)) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: TX queue: %d is full, depth: %d\n", "TX queue: %d is full, depth: %d\n",
__func__, qnum, txq->axq_depth); qnum, txq->axq_depth);
ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
txq->stopped = 1; txq->stopped = 1;
spin_unlock_bh(&txq->axq_lock); spin_unlock_bh(&txq->axq_lock);
...@@ -2047,8 +2032,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum, ...@@ -2047,8 +2032,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to update hardware queue %u!\n", "Unable to update hardware queue %u!\n", qnum);
__func__, qnum);
error = -EIO; error = -EIO;
} else { } else {
ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */ ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
...@@ -2167,7 +2151,7 @@ void ath_draintxq(struct ath_softc *sc, bool retry_tx) ...@@ -2167,7 +2151,7 @@ void ath_draintxq(struct ath_softc *sc, bool retry_tx)
* we go to INIT state */ * we go to INIT state */
if (!(sc->sc_flags & SC_OP_INVALID)) { if (!(sc->sc_flags & SC_OP_INVALID)) {
(void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__, DPRINTF(sc, ATH_DBG_XMIT, "beacon queue %x\n",
ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq)); ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
} }
...@@ -2267,8 +2251,6 @@ void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid) ...@@ -2267,8 +2251,6 @@ void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid)
struct list_head bf_head; struct list_head bf_head;
INIT_LIST_HEAD(&bf_head); INIT_LIST_HEAD(&bf_head);
DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
if (txtid->state & AGGR_CLEANUP) /* cleanup is in progress */ if (txtid->state & AGGR_CLEANUP) /* cleanup is in progress */
return; return;
...@@ -2501,8 +2483,7 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb) ...@@ -2501,8 +2483,7 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
if (hdrlen & 3) { if (hdrlen & 3) {
padsize = hdrlen % 4; padsize = hdrlen % 4;
if (skb_headroom(skb) < padsize) { if (skb_headroom(skb) < padsize) {
DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding " DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
"failed\n", __func__);
dev_kfree_skb_any(skb); dev_kfree_skb_any(skb);
return; return;
} }
...@@ -2512,12 +2493,10 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb) ...@@ -2512,12 +2493,10 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
txctl.txq = sc->sc_cabq; txctl.txq = sc->sc_cabq;
DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n", DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
__func__,
skb);
if (ath_tx_start(sc, skb, &txctl) != 0) { if (ath_tx_start(sc, skb, &txctl) != 0) {
DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__); DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
goto exit; goto exit;
} }
......
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