MIPS: Reorganize ISA constants strictly as bitmasks.

Signed-off-by: NRalf Baechle <ralf@ongar.mips.com>

include/asm-mips/cpu-features.h

@@ -116,6 +116,27 @@
 #endif
 #endif
 
+# ifndef cpu_has_mips32r1
+# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
+# endif
+# ifndef cpu_has_mips32r2
+# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
+# endif
+# ifndef cpu_has_mips64r1
+# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
+# endif
+# ifndef cpu_has_mips64r2
+# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
+# endif
+
+/*
+ * Shortcuts ...
+ */
+#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2)
+#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2)
+#define cpu_has_mips_r1	(cpu_has_mips32r1 | cpu_has_mips64r1)
+#define cpu_has_mips_r2	(cpu_has_mips32r2 | cpu_has_mips64r2)
+
 #ifndef cpu_has_dsp
 #define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)
 #endif
@@ -144,18 +165,6 @@
 # ifndef cpu_has_64bit_addresses
 # define cpu_has_64bit_addresses	0
 # endif
-# ifndef cpu_has_mips32r1
-# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
-# endif
-# ifndef cpu_has_mips32r2
-# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
-# endif
-# ifndef cpu_has_mips64r1
-# define cpu_has_mips64r1	0
-# endif
-# ifndef cpu_has_mips64r2
-# define cpu_has_mips64r2	0
-# endif
 #endif
 
 #ifdef CONFIG_64BIT
@@ -174,18 +183,6 @@
 # ifndef cpu_has_64bit_addresses
 # define cpu_has_64bit_addresses	1
 # endif
-# ifndef cpu_has_mips32r1
-# define cpu_has_mips32r1	0
-# endif
-# ifndef cpu_has_mips32r2
-# define cpu_has_mips32r2	0
-# endif
-# ifndef cpu_has_mips64r1
-# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
-# endif
-# ifndef cpu_has_mips64r2
-# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
-# endif
 #endif
 
 #ifdef CONFIG_CPU_MIPSR2

include/asm-mips/cpu.h

@@ -202,17 +202,20 @@
  * ISA Level encodings
  *
  */
-#define MIPS_CPU_ISA_64BIT	0x00008000
-
 #define MIPS_CPU_ISA_I		0x00000001
 #define MIPS_CPU_ISA_II		0x00000002
-#define MIPS_CPU_ISA_III	(0x00000003 | MIPS_CPU_ISA_64BIT)
-#define MIPS_CPU_ISA_IV		(0x00000004 | MIPS_CPU_ISA_64BIT)
-#define MIPS_CPU_ISA_V		(0x00000005 | MIPS_CPU_ISA_64BIT)
+#define MIPS_CPU_ISA_III	0x00000003
+#define MIPS_CPU_ISA_IV		0x00000004
+#define MIPS_CPU_ISA_V		0x00000005
 #define MIPS_CPU_ISA_M32R1	0x00000020
 #define MIPS_CPU_ISA_M32R2	0x00000040
-#define MIPS_CPU_ISA_M64R1	(0x00000080 | MIPS_CPU_ISA_64BIT)
-#define MIPS_CPU_ISA_M64R2	(0x00000100 | MIPS_CPU_ISA_64BIT)
+#define MIPS_CPU_ISA_M64R1	0x00000080
+#define MIPS_CPU_ISA_M64R2	0x00000100
+
+#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
+	MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
+#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
+	MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
 
 /*
  * CPU Option encodings