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029af8c7
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029af8c7
编写于
12月 14, 2008
作者:
I
Ingo Molnar
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'linus' into perfcounters/core
上级
75f224cf
5279585f
变更
17
展开全部
隐藏空白更改
内联
并排
Showing
17 changed file
with
794 addition
and
737 deletion
+794
-737
arch/mips/Kconfig.debug
arch/mips/Kconfig.debug
+1
-1
arch/mips/configs/ip32_defconfig
arch/mips/configs/ip32_defconfig
+624
-436
arch/mips/include/asm/asmmacro.h
arch/mips/include/asm/asmmacro.h
+10
-0
arch/mips/mm/dma-default.c
arch/mips/mm/dma-default.c
+3
-0
arch/powerpc/boot/Makefile
arch/powerpc/boot/Makefile
+1
-0
drivers/cdrom/cdrom.c
drivers/cdrom/cdrom.c
+10
-6
drivers/char/cp437.uni
drivers/char/cp437.uni
+6
-6
drivers/char/vt.c
drivers/char/vt.c
+1
-1
drivers/i2c/busses/i2c-highlander.c
drivers/i2c/busses/i2c-highlander.c
+2
-2
drivers/i2c/busses/i2c-pmcmsp.c
drivers/i2c/busses/i2c-pmcmsp.c
+1
-1
drivers/scsi/device_handler/scsi_dh_hp_sw.c
drivers/scsi/device_handler/scsi_dh_hp_sw.c
+8
-4
drivers/video/aty/radeon_accel.c
drivers/video/aty/radeon_accel.c
+86
-209
drivers/video/aty/radeon_backlight.c
drivers/video/aty/radeon_backlight.c
+1
-1
drivers/video/aty/radeon_base.c
drivers/video/aty/radeon_base.c
+15
-31
drivers/video/aty/radeon_pm.c
drivers/video/aty/radeon_pm.c
+3
-3
drivers/video/aty/radeonfb.h
drivers/video/aty/radeonfb.h
+17
-23
include/video/radeon.h
include/video/radeon.h
+5
-13
未找到文件。
arch/mips/Kconfig.debug
浏览文件 @
029af8c7
...
...
@@ -48,7 +48,7 @@ config RUNTIME_DEBUG
help
If you say Y here, some debugging macros will do run-time checking.
If you say N here, those macros will mostly turn to no-ops. See
include/asm-mips/debug.h for debu
ging macros.
arch/mips/include/asm/debug.h for debug
ging macros.
If unsure, say N.
endmenu
arch/mips/configs/ip32_defconfig
浏览文件 @
029af8c7
此差异已折叠。
点击以展开。
arch/mips/include/asm/asmmacro.h
浏览文件 @
029af8c7
...
...
@@ -35,6 +35,16 @@
mtc0
\
reg
,
CP0_TCSTATUS
_ehb
.
endm
#elif defined(CONFIG_CPU_MIPSR2)
.
macro
local_irq_enable
reg
=
t0
ei
irq_enable_hazard
.
endm
.
macro
local_irq_disable
reg
=
t0
di
irq_disable_hazard
.
endm
#else
.
macro
local_irq_enable
reg
=
t0
mfc0
\
reg
,
CP0_STATUS
...
...
arch/mips/mm/dma-default.c
浏览文件 @
029af8c7
...
...
@@ -111,6 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent);
void
dma_free_noncoherent
(
struct
device
*
dev
,
size_t
size
,
void
*
vaddr
,
dma_addr_t
dma_handle
)
{
plat_unmap_dma_mem
(
dma_handle
);
free_pages
((
unsigned
long
)
vaddr
,
get_order
(
size
));
}
...
...
@@ -121,6 +122,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
{
unsigned
long
addr
=
(
unsigned
long
)
vaddr
;
plat_unmap_dma_mem
(
dma_handle
);
if
(
!
plat_device_is_coherent
(
dev
))
addr
=
CAC_ADDR
(
addr
);
...
...
arch/powerpc/boot/Makefile
浏览文件 @
029af8c7
...
...
@@ -41,6 +41,7 @@ $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/ebony.o
:
BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-taishan.o
:
BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-katmai.o
:
BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-acadia.o
:
BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o
:
BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o
:
BOOTAFLAGS += -mcpu=405
...
...
drivers/cdrom/cdrom.c
浏览文件 @
029af8c7
...
...
@@ -2081,10 +2081,6 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
if
(
!
q
)
return
-
ENXIO
;
rq
=
blk_get_request
(
q
,
READ
,
GFP_KERNEL
);
if
(
!
rq
)
return
-
ENOMEM
;
cdi
->
last_sense
=
0
;
while
(
nframes
)
{
...
...
@@ -2096,9 +2092,17 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
len
=
nr
*
CD_FRAMESIZE_RAW
;
rq
=
blk_get_request
(
q
,
READ
,
GFP_KERNEL
);
if
(
!
rq
)
{
ret
=
-
ENOMEM
;
break
;
}
ret
=
blk_rq_map_user
(
q
,
rq
,
NULL
,
ubuf
,
len
,
GFP_KERNEL
);
if
(
ret
)
if
(
ret
)
{
blk_put_request
(
rq
);
break
;
}
rq
->
cmd
[
0
]
=
GPCMD_READ_CD
;
rq
->
cmd
[
1
]
=
1
<<
2
;
...
...
@@ -2124,6 +2128,7 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
if
(
blk_rq_unmap_user
(
bio
))
ret
=
-
EFAULT
;
blk_put_request
(
rq
);
if
(
ret
)
break
;
...
...
@@ -2133,7 +2138,6 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
ubuf
+=
len
;
}
blk_put_request
(
rq
);
return
ret
;
}
...
...
drivers/char/cp437.uni
浏览文件 @
029af8c7
...
...
@@ -27,7 +27,7 @@
0x0c U+2640
0x0d U+266a
0x0e U+266b
0x0f U+263c
0x0f U+263c
U+00a4
0x10 U+25b6 U+25ba
0x11 U+25c0 U+25c4
0x12 U+2195
...
...
@@ -55,7 +55,7 @@
0x24 U+0024
0x25 U+0025
0x26 U+0026
0x27 U+0027
0x27 U+0027
U+00b4
0x28 U+0028
0x29 U+0029
0x2a U+002a
...
...
@@ -84,7 +84,7 @@
0x41 U+0041 U+00c0 U+00c1 U+00c2 U+00c3
0x42 U+0042
0x43 U+0043 U+00a9
0x44 U+0044
0x44 U+0044
U+00d0
0x45 U+0045 U+00c8 U+00ca U+00cb
0x46 U+0046
0x47 U+0047
...
...
@@ -140,7 +140,7 @@
0x79 U+0079 U+00fd
0x7a U+007a
0x7b U+007b
0x7c U+007c U+00a
5
0x7c U+007c U+00a
6
0x7d U+007d
0x7e U+007e
#
...
...
@@ -263,10 +263,10 @@
0xe8 U+03a6 U+00d8
0xe9 U+0398
0xea U+03a9 U+2126
0xeb U+03b4
0xeb U+03b4
U+00f0
0xec U+221e
0xed U+03c6 U+00f8
0xee U+03b5
0xee U+03b5
U+2208
0xef U+2229
0xf0 U+2261
0xf1 U+00b1
...
...
drivers/char/vt.c
浏览文件 @
029af8c7
...
...
@@ -2274,7 +2274,7 @@ static int do_con_write(struct tty_struct *tty, const unsigned char *buf, int co
continue
;
/* nothing to display */
}
/* Glyph not found */
if
((
!
(
vc
->
vc_utf
&&
!
vc
->
vc_disp_ctrl
)
||
c
<
128
)
&&
!
(
c
&
~
charmask
))
{
if
((
!
(
vc
->
vc_utf
&&
!
vc
->
vc_disp_ctrl
)
&&
c
<
128
)
&&
!
(
c
&
~
charmask
))
{
/* In legacy mode use the glyph we get by a 1:1 mapping.
This would make absolutely no sense with Unicode in mind,
but do this for ASCII characters since a font may lack
...
...
drivers/i2c/busses/i2c-highlander.c
浏览文件 @
029af8c7
...
...
@@ -92,7 +92,7 @@ static void highlander_i2c_setup(struct highlander_i2c_dev *dev)
static
void
smbus_write_data
(
u8
*
src
,
u16
*
dst
,
int
len
)
{
for
(;
len
>
1
;
len
-=
2
)
{
*
dst
++
=
be16_to_cpup
((
u
16
*
)
src
);
*
dst
++
=
be16_to_cpup
((
__be
16
*
)
src
);
src
+=
2
;
}
...
...
@@ -103,7 +103,7 @@ static void smbus_write_data(u8 *src, u16 *dst, int len)
static
void
smbus_read_data
(
u16
*
src
,
u8
*
dst
,
int
len
)
{
for
(;
len
>
1
;
len
-=
2
)
{
*
(
u
16
*
)
dst
=
cpu_to_be16p
(
src
++
);
*
(
__be
16
*
)
dst
=
cpu_to_be16p
(
src
++
);
dst
+=
2
;
}
...
...
drivers/i2c/busses/i2c-pmcmsp.c
浏览文件 @
029af8c7
...
...
@@ -486,7 +486,7 @@ static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
if
(
cmd
->
type
==
MSP_TWI_CMD_WRITE
||
cmd
->
type
==
MSP_TWI_CMD_WRITE_READ
)
{
__be64
tmp
=
cpu_to_be64p
((
u
64
*
)
cmd
->
write_data
);
u64
tmp
=
be64_to_cpup
((
__be
64
*
)
cmd
->
write_data
);
tmp
>>=
(
MSP_MAX_BYTES_PER_RW
-
cmd
->
write_len
)
*
8
;
dev_dbg
(
&
pmcmsptwi_adapter
.
dev
,
"Writing 0x%016llx
\n
"
,
tmp
);
pmcmsptwi_writel
(
tmp
&
0x00000000ffffffffLL
,
...
...
drivers/scsi/device_handler/scsi_dh_hp_sw.c
浏览文件 @
029af8c7
...
...
@@ -107,6 +107,7 @@ static int hp_sw_tur(struct scsi_device *sdev, struct hp_sw_dh_data *h)
struct
request
*
req
;
int
ret
;
retry:
req
=
blk_get_request
(
sdev
->
request_queue
,
WRITE
,
GFP_NOIO
);
if
(
!
req
)
return
SCSI_DH_RES_TEMP_UNAVAIL
;
...
...
@@ -121,7 +122,6 @@ static int hp_sw_tur(struct scsi_device *sdev, struct hp_sw_dh_data *h)
memset
(
req
->
sense
,
0
,
SCSI_SENSE_BUFFERSIZE
);
req
->
sense_len
=
0
;
retry:
ret
=
blk_execute_rq
(
req
->
q
,
NULL
,
req
,
1
);
if
(
ret
==
-
EIO
)
{
if
(
req
->
sense_len
>
0
)
{
...
...
@@ -136,8 +136,10 @@ static int hp_sw_tur(struct scsi_device *sdev, struct hp_sw_dh_data *h)
h
->
path_state
=
HP_SW_PATH_ACTIVE
;
ret
=
SCSI_DH_OK
;
}
if
(
ret
==
SCSI_DH_IMM_RETRY
)
if
(
ret
==
SCSI_DH_IMM_RETRY
)
{
blk_put_request
(
req
);
goto
retry
;
}
if
(
ret
==
SCSI_DH_DEV_OFFLINED
)
{
h
->
path_state
=
HP_SW_PATH_PASSIVE
;
ret
=
SCSI_DH_OK
;
...
...
@@ -200,6 +202,7 @@ static int hp_sw_start_stop(struct scsi_device *sdev, struct hp_sw_dh_data *h)
struct
request
*
req
;
int
ret
,
retry
;
retry:
req
=
blk_get_request
(
sdev
->
request_queue
,
WRITE
,
GFP_NOIO
);
if
(
!
req
)
return
SCSI_DH_RES_TEMP_UNAVAIL
;
...
...
@@ -216,7 +219,6 @@ static int hp_sw_start_stop(struct scsi_device *sdev, struct hp_sw_dh_data *h)
req
->
sense_len
=
0
;
retry
=
h
->
retries
;
retry:
ret
=
blk_execute_rq
(
req
->
q
,
NULL
,
req
,
1
);
if
(
ret
==
-
EIO
)
{
if
(
req
->
sense_len
>
0
)
{
...
...
@@ -231,8 +233,10 @@ static int hp_sw_start_stop(struct scsi_device *sdev, struct hp_sw_dh_data *h)
ret
=
SCSI_DH_OK
;
if
(
ret
==
SCSI_DH_RETRY
)
{
if
(
--
retry
)
if
(
--
retry
)
{
blk_put_request
(
req
);
goto
retry
;
}
ret
=
SCSI_DH_IO
;
}
...
...
drivers/video/aty/radeon_accel.c
浏览文件 @
029af8c7
...
...
@@ -5,61 +5,61 @@
* --dte
*/
#define FLUSH_CACHE_WORKAROUND 1
void
radeon_fifo_update_and_wait
(
struct
radeonfb_info
*
rinfo
,
int
entries
)
static
void
radeon_fixup_offset
(
struct
radeonfb_info
*
rinfo
)
{
int
i
;
u32
local_base
;
/* *** Ugly workaround *** */
/*
* On some platforms, the video memory is mapped at 0 in radeon chip space
* (like PPCs) by the firmware. X will always move it up so that it's seen
* by the chip to be at the same address as the PCI BAR.
* That means that when switching back from X, there is a mismatch between
* the offsets programmed into the engine. This means that potentially,
* accel operations done before radeonfb has a chance to re-init the engine
* will have incorrect offsets, and potentially trash system memory !
*
* The correct fix is for fbcon to never call any accel op before the engine
* has properly been re-initialized (by a call to set_var), but this is a
* complex fix. This workaround in the meantime, called before every accel
* operation, makes sure the offsets are in sync.
*/
for
(
i
=
0
;
i
<
2000000
;
i
++
)
{
rinfo
->
fifo_free
=
INREG
(
RBBM_STATUS
)
&
0x7f
;
if
(
rinfo
->
fifo_free
>=
entries
)
return
;
udelay
(
10
);
}
printk
(
KERN_ERR
"radeonfb: FIFO Timeout !
\n
"
);
/* XXX Todo: attempt to reset the engine */
}
radeon_fifo_wait
(
1
);
local_base
=
INREG
(
MC_FB_LOCATION
)
<<
16
;
if
(
local_base
==
rinfo
->
fb_local_base
)
return
;
static
inline
void
radeon_fifo_wait
(
struct
radeonfb_info
*
rinfo
,
int
entries
)
{
if
(
entries
<=
rinfo
->
fifo_free
)
rinfo
->
fifo_free
-=
entries
;
else
radeon_fifo_update_and_wait
(
rinfo
,
entries
);
}
rinfo
->
fb_local_base
=
local_base
;
static
inline
void
radeonfb_set_creg
(
struct
radeonfb_info
*
rinfo
,
u32
reg
,
u32
*
cache
,
u32
new_val
)
{
if
(
new_val
==
*
cache
)
return
;
*
cache
=
new_val
;
radeon_fifo_wait
(
rinfo
,
1
);
OUTREG
(
reg
,
new_val
);
radeon_fifo_wait
(
3
);
OUTREG
(
DEFAULT_PITCH_OFFSET
,
(
rinfo
->
pitch
<<
0x16
)
|
(
rinfo
->
fb_local_base
>>
10
));
OUTREG
(
DST_PITCH_OFFSET
,
(
rinfo
->
pitch
<<
0x16
)
|
(
rinfo
->
fb_local_base
>>
10
));
OUTREG
(
SRC_PITCH_OFFSET
,
(
rinfo
->
pitch
<<
0x16
)
|
(
rinfo
->
fb_local_base
>>
10
));
}
static
void
radeonfb_prim_fillrect
(
struct
radeonfb_info
*
rinfo
,
const
struct
fb_fillrect
*
region
)
{
radeon
fb_set_creg
(
rinfo
,
DP_GUI_MASTER_CNTL
,
&
rinfo
->
dp_gui_mc_cache
,
rinfo
->
dp_gui_mc_base
|
GMC_BRUSH_SOLID_COLOR
|
ROP3_P
);
radeonfb_set_creg
(
rinfo
,
DP_CNTL
,
&
rinfo
->
dp_cntl_cache
,
DST_X_LEFT_TO_RIGHT
|
DST_Y_TOP_TO_BOTTOM
);
radeonfb_set_creg
(
rinfo
,
DP_BRUSH_FRGD_CLR
,
&
rinfo
->
dp_brush_fg_cache
,
region
->
color
);
/* Ensure the dst cache is flushed and the engine idle before
* issuing the operation.
*
* This works around engine lockups on some cards
*/
#if FLUSH_CACHE_WORKAROUND
radeon_fifo_wait
(
rinfo
,
2
);
radeon
_fifo_wait
(
4
);
OUTREG
(
DP_GUI_MASTER_CNTL
,
rinfo
->
dp_gui_master_cntl
/* contains, like GMC_DST_32BPP */
|
GMC_BRUSH_SOLID_COLOR
|
ROP3_P
);
if
(
radeon_get_dstbpp
(
rinfo
->
depth
)
!=
DST_8BPP
)
OUTREG
(
DP_BRUSH_FRGD_CLR
,
rinfo
->
pseudo_palette
[
region
->
color
]);
else
OUTREG
(
DP_BRUSH_FRGD_CLR
,
region
->
color
);
OUTREG
(
DP_WRITE_MSK
,
0xffffffff
);
OUTREG
(
DP_CNTL
,
(
DST_X_LEFT_TO_RIGHT
|
DST_Y_TOP_TO_BOTTOM
));
radeon_fifo_wait
(
2
);
OUTREG
(
DSTCACHE_CTLSTAT
,
RB2D_DC_FLUSH_ALL
);
OUTREG
(
WAIT_UNTIL
,
(
WAIT_2D_IDLECLEAN
|
WAIT_DMA_GUI_IDLE
));
#endif
radeon_fifo_wait
(
rinfo
,
2
);
radeon_fifo_wait
(
2
);
OUTREG
(
DST_Y_X
,
(
region
->
dy
<<
16
)
|
region
->
dx
);
OUTREG
(
DST_WIDTH_HEIGHT
,
(
region
->
width
<<
16
)
|
region
->
height
);
}
...
...
@@ -70,14 +70,15 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
struct
fb_fillrect
modded
;
int
vxres
,
vyres
;
WARN_ON
(
rinfo
->
gfx_mode
);
if
(
info
->
state
!=
FBINFO_STATE_RUNNING
||
rinfo
->
gfx_mode
)
if
(
info
->
state
!=
FBINFO_STATE_RUNNING
)
return
;
if
(
info
->
flags
&
FBINFO_HWACCEL_DISABLED
)
{
cfb_fillrect
(
info
,
region
);
return
;
}
radeon_fixup_offset
(
rinfo
);
vxres
=
info
->
var
.
xres_virtual
;
vyres
=
info
->
var
.
yres_virtual
;
...
...
@@ -90,10 +91,6 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
if
(
modded
.
dx
+
modded
.
width
>
vxres
)
modded
.
width
=
vxres
-
modded
.
dx
;
if
(
modded
.
dy
+
modded
.
height
>
vyres
)
modded
.
height
=
vyres
-
modded
.
dy
;
if
(
info
->
fix
.
visual
==
FB_VISUAL_TRUECOLOR
||
info
->
fix
.
visual
==
FB_VISUAL_DIRECTCOLOR
)
modded
.
color
=
((
u32
*
)
(
info
->
pseudo_palette
))[
region
->
color
];
radeonfb_prim_fillrect
(
rinfo
,
&
modded
);
}
...
...
@@ -112,22 +109,22 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
if
(
xdir
<
0
)
{
sx
+=
w
-
1
;
dx
+=
w
-
1
;
}
if
(
ydir
<
0
)
{
sy
+=
h
-
1
;
dy
+=
h
-
1
;
}
radeon
fb_set_creg
(
rinfo
,
DP_GUI_MASTER_CNTL
,
&
rinfo
->
dp_gui_mc_cache
,
rinfo
->
dp_gui_mc_base
|
GMC_BRUSH_NONE
|
GMC_SRC_DATATYPE_COLOR
|
ROP3_S
|
DP_SRC_SOURCE_MEMORY
);
radeonfb_set_creg
(
rinfo
,
DP_CNTL
,
&
rinfo
->
dp_cntl_cache
,
(
xdir
>=
0
?
DST_X_LEFT_TO_RIGHT
:
0
)
|
(
ydir
>=
0
?
DST_Y_TOP_TO_BOTTOM
:
0
));
#if FLUSH_CACHE_WORKAROUND
radeon_fifo_wait
(
rinfo
,
2
);
radeon
_fifo_wait
(
3
);
OUTREG
(
DP_GUI_MASTER_CNTL
,
rinfo
->
dp_gui_master_cntl
/* i.e. GMC_DST_32BPP */
|
GMC_BRUSH_NONE
|
GMC_SRC_DSTCOLOR
|
ROP3_S
|
DP_SRC_SOURCE_MEMORY
);
OUTREG
(
DP_WRITE_MSK
,
0xffffffff
);
OUTREG
(
DP_CNTL
,
(
xdir
>=
0
?
DST_X_LEFT_TO_RIGHT
:
0
)
|
(
ydir
>=
0
?
DST_Y_TOP_TO_BOTTOM
:
0
));
radeon_fifo_wait
(
2
);
OUTREG
(
DSTCACHE_CTLSTAT
,
RB2D_DC_FLUSH_ALL
);
OUTREG
(
WAIT_UNTIL
,
(
WAIT_2D_IDLECLEAN
|
WAIT_DMA_GUI_IDLE
));
#endif
radeon_fifo_wait
(
rinfo
,
3
);
radeon_fifo_wait
(
3
);
OUTREG
(
SRC_Y_X
,
(
sy
<<
16
)
|
sx
);
OUTREG
(
DST_Y_X
,
(
dy
<<
16
)
|
dx
);
OUTREG
(
DST_HEIGHT_WIDTH
,
(
h
<<
16
)
|
w
);
...
...
@@ -146,14 +143,15 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
modded
.
width
=
area
->
width
;
modded
.
height
=
area
->
height
;
WARN_ON
(
rinfo
->
gfx_mode
);
if
(
info
->
state
!=
FBINFO_STATE_RUNNING
||
rinfo
->
gfx_mode
)
if
(
info
->
state
!=
FBINFO_STATE_RUNNING
)
return
;
if
(
info
->
flags
&
FBINFO_HWACCEL_DISABLED
)
{
cfb_copyarea
(
info
,
area
);
return
;
}
radeon_fixup_offset
(
rinfo
);
vxres
=
info
->
var
.
xres_virtual
;
vyres
=
info
->
var
.
yres_virtual
;
...
...
@@ -170,116 +168,13 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
radeonfb_prim_copyarea
(
rinfo
,
&
modded
);
}
static
void
radeonfb_prim_imageblit
(
struct
radeonfb_info
*
rinfo
,
const
struct
fb_image
*
image
,
u32
fg
,
u32
bg
)
{
unsigned
int
dwords
;
u32
*
bits
;
radeonfb_set_creg
(
rinfo
,
DP_GUI_MASTER_CNTL
,
&
rinfo
->
dp_gui_mc_cache
,
rinfo
->
dp_gui_mc_base
|
GMC_BRUSH_NONE
|
GMC_DST_CLIP_LEAVE
|
GMC_SRC_DATATYPE_MONO_FG_BG
|
ROP3_S
|
GMC_BYTE_ORDER_MSB_TO_LSB
|
DP_SRC_SOURCE_HOST_DATA
);
radeonfb_set_creg
(
rinfo
,
DP_CNTL
,
&
rinfo
->
dp_cntl_cache
,
DST_X_LEFT_TO_RIGHT
|
DST_Y_TOP_TO_BOTTOM
);
radeonfb_set_creg
(
rinfo
,
DP_SRC_FRGD_CLR
,
&
rinfo
->
dp_src_fg_cache
,
fg
);
radeonfb_set_creg
(
rinfo
,
DP_SRC_BKGD_CLR
,
&
rinfo
->
dp_src_bg_cache
,
bg
);
/* Ensure the dst cache is flushed and the engine idle before
* issuing the operation.
*
* This works around engine lockups on some cards
*/
#if FLUSH_CACHE_WORKAROUND
radeon_fifo_wait
(
rinfo
,
2
);
OUTREG
(
DSTCACHE_CTLSTAT
,
RB2D_DC_FLUSH_ALL
);
OUTREG
(
WAIT_UNTIL
,
(
WAIT_2D_IDLECLEAN
|
WAIT_DMA_GUI_IDLE
));
#endif
/* X here pads width to a multiple of 32 and uses the clipper to
* adjust the result. Is that really necessary ? Things seem to
* work ok for me without that and the doco doesn't seem to imply]
* there is such a restriction.
*/
radeon_fifo_wait
(
rinfo
,
4
);
OUTREG
(
SC_TOP_LEFT
,
(
image
->
dy
<<
16
)
|
image
->
dx
);
OUTREG
(
SC_BOTTOM_RIGHT
,
((
image
->
dy
+
image
->
height
)
<<
16
)
|
(
image
->
dx
+
image
->
width
));
OUTREG
(
DST_Y_X
,
(
image
->
dy
<<
16
)
|
image
->
dx
);
OUTREG
(
DST_HEIGHT_WIDTH
,
(
image
->
height
<<
16
)
|
((
image
->
width
+
31
)
&
~
31
));
dwords
=
(
image
->
width
+
31
)
>>
5
;
dwords
*=
image
->
height
;
bits
=
(
u32
*
)(
image
->
data
);
while
(
dwords
>=
8
)
{
radeon_fifo_wait
(
rinfo
,
8
);
#if BITS_PER_LONG == 64
__raw_writeq
(
*
((
u64
*
)(
bits
)),
rinfo
->
mmio_base
+
HOST_DATA0
);
__raw_writeq
(
*
((
u64
*
)(
bits
+
2
)),
rinfo
->
mmio_base
+
HOST_DATA2
);
__raw_writeq
(
*
((
u64
*
)(
bits
+
4
)),
rinfo
->
mmio_base
+
HOST_DATA4
);
__raw_writeq
(
*
((
u64
*
)(
bits
+
6
)),
rinfo
->
mmio_base
+
HOST_DATA6
);
bits
+=
8
;
#else
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA0
);
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA1
);
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA2
);
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA3
);
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA4
);
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA5
);
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA6
);
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA7
);
#endif
dwords
-=
8
;
}
while
(
dwords
--
)
{
radeon_fifo_wait
(
rinfo
,
1
);
__raw_writel
(
*
(
bits
++
),
rinfo
->
mmio_base
+
HOST_DATA0
);
}
}
void
radeonfb_imageblit
(
struct
fb_info
*
info
,
const
struct
fb_image
*
image
)
{
struct
radeonfb_info
*
rinfo
=
info
->
par
;
u32
fg
,
bg
;
WARN_ON
(
rinfo
->
gfx_mode
);
if
(
info
->
state
!=
FBINFO_STATE_RUNNING
||
rinfo
->
gfx_mode
)
return
;
if
(
!
image
->
width
||
!
image
->
height
)
if
(
info
->
state
!=
FBINFO_STATE_RUNNING
)
return
;
/* We only do 1 bpp color expansion for now */
if
(
!
accel_cexp
||
(
info
->
flags
&
FBINFO_HWACCEL_DISABLED
)
||
image
->
depth
!=
1
)
goto
fallback
;
/* Fallback if running out of the screen. We may do clipping
* in the future */
if
((
image
->
dx
+
image
->
width
)
>
info
->
var
.
xres_virtual
||
(
image
->
dy
+
image
->
height
)
>
info
->
var
.
yres_virtual
)
goto
fallback
;
if
(
info
->
fix
.
visual
==
FB_VISUAL_TRUECOLOR
||
info
->
fix
.
visual
==
FB_VISUAL_DIRECTCOLOR
)
{
fg
=
((
u32
*
)(
info
->
pseudo_palette
))[
image
->
fg_color
];
bg
=
((
u32
*
)(
info
->
pseudo_palette
))[
image
->
bg_color
];
}
else
{
fg
=
image
->
fg_color
;
bg
=
image
->
bg_color
;
}
radeonfb_prim_imageblit
(
rinfo
,
image
,
fg
,
bg
);
return
;
fallback:
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
cfb_imageblit
(
info
,
image
);
}
...
...
@@ -290,8 +185,7 @@ int radeonfb_sync(struct fb_info *info)
if
(
info
->
state
!=
FBINFO_STATE_RUNNING
)
return
0
;
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
return
0
;
}
...
...
@@ -367,10 +261,9 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
/* disable 3D engine */
OUTREG
(
RB3D_CNTL
,
0
);
rinfo
->
fifo_free
=
0
;
radeonfb_engine_reset
(
rinfo
);
radeon_fifo_wait
(
rinfo
,
1
);
radeon_fifo_wait
(
1
);
if
(
IS_R300_VARIANT
(
rinfo
))
{
OUTREG
(
RB2D_DSTCACHE_MODE
,
INREG
(
RB2D_DSTCACHE_MODE
)
|
RB2D_DC_AUTOFLUSH_ENABLE
|
...
...
@@ -384,7 +277,7 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
OUTREG
(
RB2D_DSTCACHE_MODE
,
0
);
}
radeon_fifo_wait
(
rinfo
,
3
);
radeon_fifo_wait
(
3
);
/* We re-read MC_FB_LOCATION from card as it can have been
* modified by XFree drivers (ouch !)
*/
...
...
@@ -395,57 +288,41 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
OUTREG
(
DST_PITCH_OFFSET
,
(
rinfo
->
pitch
<<
0x16
)
|
(
rinfo
->
fb_local_base
>>
10
));
OUTREG
(
SRC_PITCH_OFFSET
,
(
rinfo
->
pitch
<<
0x16
)
|
(
rinfo
->
fb_local_base
>>
10
));
radeon_fifo_wait
(
rinfo
,
1
);
#if
def __BIG_ENDIAN
radeon_fifo_wait
(
1
);
#if
defined(__BIG_ENDIAN)
OUTREGP
(
DP_DATATYPE
,
HOST_BIG_ENDIAN_EN
,
~
HOST_BIG_ENDIAN_EN
);
#else
OUTREGP
(
DP_DATATYPE
,
0
,
~
HOST_BIG_ENDIAN_EN
);
#endif
radeon_fifo_wait
(
rinfo
,
2
);
radeon_fifo_wait
(
2
);
OUTREG
(
DEFAULT_SC_TOP_LEFT
,
0
);
OUTREG
(
DEFAULT_SC_BOTTOM_RIGHT
,
(
DEFAULT_SC_RIGHT_MAX
|
DEFAULT_SC_BOTTOM_MAX
));
/* set default DP_GUI_MASTER_CNTL */
temp
=
radeon_get_dstbpp
(
rinfo
->
depth
);
rinfo
->
dp_gui_m
c_base
=
((
temp
<<
8
)
|
GMC_CLR_CMP_CNTL_DIS
);
rinfo
->
dp_gui_m
aster_cntl
=
((
temp
<<
8
)
|
GMC_CLR_CMP_CNTL_DIS
);
rinfo
->
dp_gui_mc_cache
=
rinfo
->
dp_gui_mc_base
|
GMC_BRUSH_SOLID_COLOR
|
GMC_SRC_DATATYPE_COLOR
;
radeon_fifo_wait
(
rinfo
,
1
);
OUTREG
(
DP_GUI_MASTER_CNTL
,
rinfo
->
dp_gui_mc_cache
);
radeon_fifo_wait
(
1
);
OUTREG
(
DP_GUI_MASTER_CNTL
,
(
rinfo
->
dp_gui_master_cntl
|
GMC_BRUSH_SOLID_COLOR
|
GMC_SRC_DATATYPE_COLOR
));
radeon_fifo_wait
(
7
);
/* clear line drawing regs */
radeon_fifo_wait
(
rinfo
,
2
);
OUTREG
(
DST_LINE_START
,
0
);
OUTREG
(
DST_LINE_END
,
0
);
/* set brush and source color regs */
rinfo
->
dp_brush_fg_cache
=
0xffffffff
;
rinfo
->
dp_brush_bg_cache
=
0x00000000
;
rinfo
->
dp_src_fg_cache
=
0xffffffff
;
rinfo
->
dp_src_bg_cache
=
0x00000000
;
radeon_fifo_wait
(
rinfo
,
4
);
OUTREG
(
DP_BRUSH_FRGD_CLR
,
rinfo
->
dp_brush_fg_cache
);
OUTREG
(
DP_BRUSH_BKGD_CLR
,
rinfo
->
dp_brush_bg_cache
);
OUTREG
(
DP_SRC_FRGD_CLR
,
rinfo
->
dp_src_fg_cache
);
OUTREG
(
DP_SRC_BKGD_CLR
,
rinfo
->
dp_src_bg_cache
);
/* Default direction */
rinfo
->
dp_cntl_cache
=
DST_X_LEFT_TO_RIGHT
|
DST_Y_TOP_TO_BOTTOM
;
radeon_fifo_wait
(
rinfo
,
1
);
OUTREG
(
DP_CNTL
,
rinfo
->
dp_cntl_cache
);
/* set brush color regs */
OUTREG
(
DP_BRUSH_FRGD_CLR
,
0xffffffff
);
OUTREG
(
DP_BRUSH_BKGD_CLR
,
0x00000000
);
/* set source color regs */
OUTREG
(
DP_SRC_FRGD_CLR
,
0xffffffff
);
OUTREG
(
DP_SRC_BKGD_CLR
,
0x00000000
);
/* default write mask */
radeon_fifo_wait
(
rinfo
,
1
);
OUTREG
(
DP_WRITE_MSK
,
0xffffffff
);
/* Default to no swapping of host data */
radeon_fifo_wait
(
rinfo
,
1
);
OUTREG
(
RBBM_GUICNTL
,
RBBM_GUICNTL_HOST_DATA_SWAP_NONE
);
/* Make sure it's settled */
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
}
drivers/video/aty/radeon_backlight.c
浏览文件 @
029af8c7
...
...
@@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd)
level
=
bd
->
props
.
brightness
;
del_timer_sync
(
&
rinfo
->
lvds_timer
);
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
lvds_gen_cntl
=
INREG
(
LVDS_GEN_CNTL
);
if
(
level
>
0
)
{
...
...
drivers/video/aty/radeon_base.c
浏览文件 @
029af8c7
...
...
@@ -282,8 +282,6 @@ static int backlight = 1;
static
int
backlight
=
0
;
#endif
int
accel_cexp
=
0
;
/*
* prototypes
*/
...
...
@@ -854,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var,
if
(
rinfo
->
asleep
)
return
0
;
radeon_fifo_wait
(
2
);
OUTREG
(
CRTC_OFFSET
,
((
var
->
yoffset
*
var
->
xres_virtual
+
var
->
xoffset
)
*
var
->
bits_per_pixel
/
8
)
&
~
7
);
return
0
;
...
...
@@ -883,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
if
(
rc
)
return
rc
;
radeon_fifo_wait
(
2
);
if
(
value
&
0x01
)
{
tmp
=
INREG
(
LVDS_GEN_CNTL
);
...
...
@@ -940,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
if
(
rinfo
->
lock_blank
)
return
0
;
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
val
=
INREG
(
CRTC_EXT_CNTL
);
val
&=
~
(
CRTC_DISPLAY_DIS
|
CRTC_HSYNC_DIS
|
...
...
@@ -1048,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info)
if
(
rinfo
->
asleep
)
return
0
;
return
radeon_screen_blank
(
rinfo
,
blank
,
0
);
}
...
...
@@ -1074,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
pindex
=
regno
;
if
(
!
rinfo
->
asleep
)
{
radeon_fifo_wait
(
9
);
if
(
rinfo
->
bpp
==
16
)
{
pindex
=
regno
*
8
;
...
...
@@ -1242,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
{
int
i
;
radeon_fifo_wait
(
20
);
/* Workaround from XFree */
if
(
rinfo
->
is_mobility
)
{
/* A temporal workaround for the occational blanking on certain laptop
...
...
@@ -1337,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data)
{
struct
radeonfb_info
*
rinfo
=
(
struct
radeonfb_info
*
)
data
;
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
OUTREG
(
LVDS_GEN_CNTL
,
rinfo
->
pending_lvds_gen_cntl
);
}
...
...
@@ -1355,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
if
(
nomodeset
)
return
;
radeon_engine_idle
(
rinfo
);
if
(
!
regs_only
)
radeon_screen_blank
(
rinfo
,
FB_BLANK_NORMAL
,
0
);
radeon_fifo_wait
(
31
);
for
(
i
=
0
;
i
<
10
;
i
++
)
OUTREG
(
common_regs
[
i
].
reg
,
common_regs
[
i
].
val
);
...
...
@@ -1387,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
radeon_write_pll_regs
(
rinfo
,
mode
);
if
((
primary_mon
==
MT_DFP
)
||
(
primary_mon
==
MT_LCD
))
{
radeon_fifo_wait
(
10
);
OUTREG
(
FP_CRTC_H_TOTAL_DISP
,
mode
->
fp_crtc_h_total_disp
);
OUTREG
(
FP_CRTC_V_TOTAL_DISP
,
mode
->
fp_crtc_v_total_disp
);
OUTREG
(
FP_H_SYNC_STRT_WID
,
mode
->
fp_h_sync_strt_wid
);
...
...
@@ -1401,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
if
(
!
regs_only
)
radeon_screen_blank
(
rinfo
,
FB_BLANK_UNBLANK
,
0
);
radeon_fifo_wait
(
2
);
OUTPLL
(
VCLK_ECP_CNTL
,
mode
->
vclk_ecp_cntl
);
return
;
...
...
@@ -1551,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info)
/* We always want engine to be idle on a mode switch, even
* if we won't actually change the mode
*/
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
hSyncStart
=
mode
->
xres
+
mode
->
right_margin
;
hSyncEnd
=
hSyncStart
+
mode
->
hsync_len
;
...
...
@@ -1846,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info)
return
0
;
}
static
struct
fb_ops
radeonfb_ops
=
{
.
owner
=
THIS_MODULE
,
.
fb_check_var
=
radeonfb_check_var
,
...
...
@@ -1869,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info
->
par
=
rinfo
;
info
->
pseudo_palette
=
rinfo
->
pseudo_palette
;
info
->
flags
=
FBINFO_DEFAULT
|
FBINFO_HWACCEL_IMAGEBLIT
|
FBINFO_HWACCEL_COPYAREA
|
FBINFO_HWACCEL_FILLRECT
|
FBINFO_HWACCEL_XPAN
...
...
@@ -1877,7 +1882,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info
->
fbops
=
&
radeonfb_ops
;
info
->
screen_base
=
rinfo
->
fb_base
;
info
->
screen_size
=
rinfo
->
mapped_vram
;
/* Fill fix common fields */
strlcpy
(
info
->
fix
.
id
,
rinfo
->
name
,
sizeof
(
info
->
fix
.
id
));
info
->
fix
.
smem_start
=
rinfo
->
fb_base_phys
;
...
...
@@ -1892,25 +1896,8 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info
->
fix
.
mmio_len
=
RADEON_REGSIZE
;
info
->
fix
.
accel
=
FB_ACCEL_ATI_RADEON
;
/* Allocate colormap */
fb_alloc_cmap
(
&
info
->
cmap
,
256
,
0
);
/* Setup pixmap used for acceleration */
#define PIXMAP_SIZE (2048 * 4)
info
->
pixmap
.
addr
=
kmalloc
(
PIXMAP_SIZE
,
GFP_KERNEL
);
if
(
!
info
->
pixmap
.
addr
)
{
printk
(
KERN_ERR
"radeonfb: Failed to allocate pixmap !
\n
"
);
noaccel
=
1
;
goto
bail
;
}
info
->
pixmap
.
size
=
PIXMAP_SIZE
;
info
->
pixmap
.
flags
=
FB_PIXMAP_SYSTEM
;
info
->
pixmap
.
scan_align
=
4
;
info
->
pixmap
.
buf_align
=
4
;
info
->
pixmap
.
access_align
=
32
;
bail:
if
(
noaccel
)
info
->
flags
|=
FBINFO_HWACCEL_DISABLED
;
...
...
@@ -2019,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
u32
tom
=
INREG
(
NB_TOM
);
tmp
=
((((
tom
>>
16
)
-
(
tom
&
0xffff
)
+
1
)
<<
6
)
*
1024
);
radeon_fifo_wait
(
6
);
OUTREG
(
MC_FB_LOCATION
,
tom
);
OUTREG
(
DISPLAY_BASE_ADDR
,
(
tom
&
0xffff
)
<<
16
);
OUTREG
(
CRTC2_DISPLAY_BASE_ADDR
,
(
tom
&
0xffff
)
<<
16
);
...
...
@@ -2522,8 +2510,6 @@ static int __init radeonfb_setup (char *options)
}
else
if
(
!
strncmp
(
this_opt
,
"ignore_devlist"
,
14
))
{
ignore_devlist
=
1
;
#endif
}
else
if
(
!
strncmp
(
this_opt
,
"accel_cexp"
,
12
))
{
accel_cexp
=
1
;
}
else
mode_option
=
this_opt
;
}
...
...
@@ -2571,8 +2557,6 @@ module_param(monitor_layout, charp, 0);
MODULE_PARM_DESC
(
monitor_layout
,
"Specify monitor mapping (like XFree86)"
);
module_param
(
force_measure_pll
,
bool
,
0
);
MODULE_PARM_DESC
(
force_measure_pll
,
"Force measurement of PLL (debug)"
);
module_param
(
accel_cexp
,
bool
,
0
);
MODULE_PARM_DESC
(
accel_cexp
,
"Use acceleration engine for color expansion"
);
#ifdef CONFIG_MTRR
module_param
(
nomtrr
,
bool
,
0
);
MODULE_PARM_DESC
(
nomtrr
,
"bool: disable use of MTRR registers"
);
...
...
drivers/video/aty/radeon_pm.c
浏览文件 @
029af8c7
...
...
@@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
if
(
!
(
info
->
flags
&
FBINFO_HWACCEL_DISABLED
))
{
/* Make sure engine is reset */
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
radeonfb_engine_reset
(
rinfo
);
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
}
/* Blank display and LCD */
...
...
@@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
rinfo
->
asleep
=
0
;
}
else
radeon_engine_idle
(
rinfo
);
radeon_engine_idle
();
/* Restore display & engine */
radeon_write_mode
(
rinfo
,
&
rinfo
->
state
,
1
);
...
...
drivers/video/aty/radeonfb.h
浏览文件 @
029af8c7
...
...
@@ -336,15 +336,7 @@ struct radeonfb_info {
int
mon2_type
;
u8
*
mon2_EDID
;
/* accel bits */
u32
dp_gui_mc_base
;
u32
dp_gui_mc_cache
;
u32
dp_cntl_cache
;
u32
dp_brush_fg_cache
;
u32
dp_brush_bg_cache
;
u32
dp_src_fg_cache
;
u32
dp_src_bg_cache
;
u32
fifo_free
;
u32
dp_gui_master_cntl
;
struct
pll_info
pll
;
...
...
@@ -356,7 +348,6 @@ struct radeonfb_info {
int
lock_blank
;
int
dynclk
;
int
no_schedule
;
int
gfx_mode
;
enum
radeon_pm_mode
pm_mode
;
reinit_function_ptr
reinit_func
;
...
...
@@ -401,14 +392,8 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
#define INREG16(addr) readw((rinfo->mmio_base)+addr)
#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
#ifdef CONFIG_PPC
#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
#else
#define INREG(addr) readl((rinfo->mmio_base)+addr)
#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
#endif
static
inline
void
_OUTREGP
(
struct
radeonfb_info
*
rinfo
,
u32
addr
,
u32
val
,
u32
mask
)
...
...
@@ -550,7 +535,17 @@ static inline u32 radeon_get_dstbpp(u16 depth)
* 2D Engine helper routines
*/
extern
void
radeon_fifo_update_and_wait
(
struct
radeonfb_info
*
rinfo
,
int
entries
);
static
inline
void
_radeon_fifo_wait
(
struct
radeonfb_info
*
rinfo
,
int
entries
)
{
int
i
;
for
(
i
=
0
;
i
<
2000000
;
i
++
)
{
if
((
INREG
(
RBBM_STATUS
)
&
0x7f
)
>=
entries
)
return
;
udelay
(
1
);
}
printk
(
KERN_ERR
"radeonfb: FIFO Timeout !
\n
"
);
}
static
inline
void
radeon_engine_flush
(
struct
radeonfb_info
*
rinfo
)
{
...
...
@@ -563,7 +558,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
/* Ensure FIFO is empty, ie, make sure the flush commands
* has reached the cache
*/
radeon_fifo_update_and_wait
(
rinfo
,
64
);
_radeon_fifo_wait
(
rinfo
,
64
);
/* Wait for the flush to complete */
for
(
i
=
0
;
i
<
2000000
;
i
++
)
{
...
...
@@ -575,12 +570,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
}
static
inline
void
radeon_engine_idle
(
struct
radeonfb_info
*
rinfo
)
static
inline
void
_
radeon_engine_idle
(
struct
radeonfb_info
*
rinfo
)
{
int
i
;
/* ensure FIFO is empty before waiting for idle */
radeon_fifo_update_and
_wait
(
rinfo
,
64
);
_radeon_fifo
_wait
(
rinfo
,
64
);
for
(
i
=
0
;
i
<
2000000
;
i
++
)
{
if
(((
INREG
(
RBBM_STATUS
)
&
GUI_ACTIVE
))
==
0
)
{
...
...
@@ -593,6 +588,8 @@ static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
}
#define radeon_engine_idle() _radeon_engine_idle(rinfo)
#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
...
...
@@ -622,7 +619,6 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
extern
int
radeonfb_sync
(
struct
fb_info
*
info
);
extern
void
radeonfb_engine_init
(
struct
radeonfb_info
*
rinfo
);
extern
void
radeonfb_engine_reset
(
struct
radeonfb_info
*
rinfo
);
extern
void
radeon_fixup_mem_offset
(
struct
radeonfb_info
*
rinfo
);
/* Other functions */
extern
int
radeon_screen_blank
(
struct
radeonfb_info
*
rinfo
,
int
blank
,
int
mode_switch
);
...
...
@@ -638,6 +634,4 @@ static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
static
inline
void
radeonfb_bl_exit
(
struct
radeonfb_info
*
rinfo
)
{}
#endif
extern
int
accel_cexp
;
#endif
/* __RADEONFB_H__ */
include/video/radeon.h
浏览文件 @
029af8c7
...
...
@@ -525,9 +525,6 @@
#define CRTC_DISPLAY_DIS (1 << 10)
#define CRTC_CRT_ON (1 << 15)
/* DSTCACHE_MODE bits constants */
#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8)
#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17)
/* DSTCACHE_CTLSTAT bit constants */
#define RB2D_DC_FLUSH_2D (1 << 0)
...
...
@@ -869,10 +866,15 @@
#define GMC_DST_16BPP_YVYU422 0x00000c00
#define GMC_DST_32BPP_AYUV444 0x00000e00
#define GMC_DST_16BPP_ARGB4444 0x00000f00
#define GMC_SRC_MONO 0x00000000
#define GMC_SRC_MONO_LBKGD 0x00001000
#define GMC_SRC_DSTCOLOR 0x00003000
#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
#define GMC_DP_CONVERSION_TEMP_9300 0x00008000
#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
#define GMC_DP_SRC_RECT 0x02000000
#define GMC_DP_SRC_HOST 0x03000000
#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
#define GMC_3D_FCN_EN_CLR 0x00000000
#define GMC_3D_FCN_EN_SET 0x08000000
...
...
@@ -883,9 +885,6 @@
#define GMC_WRITE_MASK_LEAVE 0x00000000
#define GMC_WRITE_MASK_SET 0x40000000
#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
#define GMC_SRC_DATATYPE_MASK (3 << 12)
#define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
#define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
#define GMC_SRC_DATATYPE_COLOR (3 << 12)
#define ROP3_S 0x00cc0000
#define ROP3_SRCCOPY 0x00cc0000
...
...
@@ -894,7 +893,6 @@
#define DP_SRC_SOURCE_MASK (7 << 24)
#define GMC_BRUSH_NONE (15 << 4)
#define DP_SRC_SOURCE_MEMORY (2 << 24)
#define DP_SRC_SOURCE_HOST_DATA (3 << 24)
#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
/* DP_MIX bit constants */
...
...
@@ -980,12 +978,6 @@
#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
/* RBBM_GUICNTL constants */
#define RBBM_GUICNTL_HOST_DATA_SWAP_NONE (0 << 0)
#define RBBM_GUICNTL_HOST_DATA_SWAP_16BIT (1 << 0)
#define RBBM_GUICNTL_HOST_DATA_SWAP_32BIT (2 << 0)
#define RBBM_GUICNTL_HOST_DATA_SWAP_HDW (3 << 0)
/* masks */
#define CONFIG_MEMSIZE_MASK 0x1f000000
...
...
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