serial: sh-sci: Move SCSCR_INIT in to platform data.

This moves all of the SCSCR_INIT definitions in to the platform data,
for future consolidation.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

arch/sh/kernel/cpu/sh2/setup-sh7619.c

@@ -63,16 +63,19 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xf8400000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 88, 88, 88, 88 },
 	}, {
 		.mapbase	= 0xf8410000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 92, 92, 92, 92 },
 	}, {
 		.mapbase	= 0xf8420000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 96, 96, 96, 96 },
 	}, {

arch/sh/kernel/cpu/sh2a/setup-mxg.c

@@ -211,6 +211,7 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xff804000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 220, 220, 220, 220 },
 	}, {

arch/sh/kernel/cpu/sh2a/setup-sh7201.c

@@ -181,41 +181,49 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xfffe8000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 180, 180, 180, 180 }
 	}, {
 		.mapbase	= 0xfffe8800,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 184, 184, 184, 184 }
 	}, {
 		.mapbase	= 0xfffe9000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 188, 188, 188, 188 }
 	}, {
 		.mapbase	= 0xfffe9800,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 192, 192, 192, 192 }
 	}, {
 		.mapbase	= 0xfffea000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 196, 196, 196, 196 }
 	}, {
 		.mapbase	= 0xfffea800,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 200, 200, 200, 200 }
 	}, {
 		.mapbase	= 0xfffeb000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 204, 204, 204, 204 }
 	}, {
 		.mapbase	= 0xfffeb800,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 208, 208, 208, 208 }
 	}, {

arch/sh/kernel/cpu/sh2a/setup-sh7203.c

@@ -177,21 +177,25 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xfffe8000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		=  { 192, 192, 192, 192 },
 	}, {
 		.mapbase	= 0xfffe8800,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		=  { 196, 196, 196, 196 },
 	}, {
 		.mapbase	= 0xfffe9000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		=  { 200, 200, 200, 200 },
 	}, {
 		.mapbase	= 0xfffe9800,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		=  { 204, 204, 204, 204 },
 	}, {

arch/sh/kernel/cpu/sh2a/setup-sh7206.c

@@ -137,21 +137,25 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xfffe8000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 240, 240, 240, 240 },
 	}, {
 		.mapbase	= 0xfffe8800,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 244, 244, 244, 244 },
 	}, {
 		.mapbase	= 0xfffe9000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 248, 248, 248, 248 },
 	}, {
 		.mapbase	= 0xfffe9800,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 252, 252, 252, 252 },
 	}, {

arch/sh/kernel/cpu/sh3/setup-sh7705.c

@@ -71,11 +71,14 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xa4410000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_TIE | SCSCR_RIE  | SCSCR_TE |
+				  SCSCR_RE  | SCSCR_CKE1 | SCSCR_CKE0,
 		.type		= PORT_SCIF,
 		.irqs		= { 56, 56, 56 },
 	}, {
 		.mapbase	= 0xa4400000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 52, 52 },
 	}, {

arch/sh/kernel/cpu/sh3/setup-sh770x.c

@@ -110,6 +110,7 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xfffffe80,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_TE | SCSCR_RE,
 		.type		= PORT_SCI,
 		.irqs		= { 23, 23, 23, 0 },
 	},
@@ -119,6 +120,7 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xa4000150,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_TE | SCSCR_RE,
 		.type		= PORT_SCIF,
 		.irqs		= { 56, 56, 56, 56 },
 	},
@@ -128,6 +130,7 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xa4000140,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_TE | SCSCR_RE,
 		.type		= PORT_IRDA,
 		.irqs		= { 52, 52, 52, 52 },
 	},

arch/sh/kernel/cpu/sh3/setup-sh7710.c

@@ -100,11 +100,15 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xa4400000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_TE | SCSCR_RE | SCSCR_REIE |
+				  SCSCR_CKE1 | SCSCR_CKE0,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 52, 52, 52 },
 	}, {
 		.mapbase	= 0xa4410000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_TE | SCSCR_RE | SCSCR_REIE |
+				  SCSCR_CKE1 | SCSCR_CKE0,
 		.type		= PORT_SCIF,
 		.irqs           = { 56, 56, 56, 56 },
 	}, {

arch/sh/kernel/cpu/sh3/setup-sh7720.c

 /*
- * SH7720 Setup
+ * Setup code for SH7720, SH7721.
  *
  *  Copyright (C) 2007  Markus Brunner, Mark Jonas
  *  Copyright (C) 2009  Paul Mundt
@@ -52,15 +52,16 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xa4430000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE,
 		.type		= PORT_SCIF,
 		.irqs		= { 80, 80, 80, 80 },
 	}, {
 		.mapbase	= 0xa4438000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE,
 		.type		= PORT_SCIF,
 		.irqs           = { 81, 81, 81, 81 },
 	}, {
-
 		.flags = 0,
 	}
 };

arch/sh/kernel/cpu/sh4/setup-sh4-202.c

@@ -19,6 +19,7 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffe80000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 41, 43, 42 },
 	}, {

arch/sh/kernel/cpu/sh4/setup-sh7750.c

@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <linux/sh_timer.h>
 #include <linux/serial_sci.h>
+#include <asm/machtypes.h>
 
 static struct resource rtc_resources[] = {
 	[0] = {
@@ -35,32 +36,36 @@ static struct platform_device rtc_device = {
 	.resource	= rtc_resources,
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-	{
-#ifndef CONFIG_SH_RTS7751R2D
-		.mapbase	= 0xffe00000,
-		.flags		= UPF_BOOT_AUTOCONF,
-		.type		= PORT_SCI,
-		.irqs		= { 23, 23, 23, 0 },
-	}, {
-#endif
-		.mapbase	= 0xffe80000,
-		.flags		= UPF_BOOT_AUTOCONF,
-		.type		= PORT_SCIF,
-		.irqs		= { 40, 40, 40, 40 },
-	}, {
-		.flags = 0,
-	}
+static struct plat_sci_port sci_platform_data = {
+	.mapbase	= 0xffe00000,
+	.flags		= UPF_BOOT_AUTOCONF,
+	.type		= PORT_SCI,
+	.scscr		= SCSCR_TE | SCSCR_RE,
+	.irqs		= { 23, 23, 23, 0 },
 };
 
 static struct platform_device sci_device = {
 	.name		= "sh-sci",
-	.id		= -1,
 	.dev		= {
 		.platform_data	= sci_platform_data,
 	},
 };
 
+static struct plat_sci_port scif_platform_data = {
+	.mapbase	= 0xffe80000,
+	.flags		= UPF_BOOT_AUTOCONF,
+	.scscr		= SCSCR_TE | SCSCR_RE | SCSCR_REIE,
+	.type		= PORT_SCIF,
+	.irqs		= { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif_device = {
+	.name		= "sh-sci",
+	.dev		= {
+		.platform_data	= scif_platform_data,
+	},
+};
+
 static struct sh_timer_config tmu0_platform_data = {
 	.name = "TMU0",
 	.channel_offset = 0x04,
@@ -222,7 +227,6 @@ static struct platform_device tmu4_device = {
 
 static struct platform_device *sh7750_devices[] __initdata = {
 	&rtc_device,
-	&sci_device,
 	&tmu0_device,
 	&tmu1_device,
 	&tmu2_device,
@@ -236,6 +240,14 @@ static struct platform_device *sh7750_devices[] __initdata = {
 
 static int __init sh7750_devices_setup(void)
 {
+	if (mach_is_rts7751r2d()) {
+		scif_platform_data.scscr |= SCSCR_CKE1;
+		platform_register_device(&scif_device);
+	} else {
+		platform_register_device(&sci_device);
+		platform_register_device(&scif_device);
+	}
+
 	return platform_add_devices(sh7750_devices,
 				    ARRAY_SIZE(sh7750_devices));
 }

arch/sh/kernel/cpu/sh4/setup-sh7760.c

@@ -130,21 +130,25 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xfe600000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 53, 55, 54 },
 	}, {
 		.mapbase	= 0xfe610000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 72, 73, 75, 74 },
 	}, {
 		.mapbase	= 0xfe620000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 76, 77, 79, 78 },
 	}, {
 		.mapbase	= 0xfe480000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCI,
 		.irqs		= { 80, 81, 82, 0 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

@@ -269,24 +269,28 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 80, 80, 80, 80 },
 		.clk		= "scif0",
 	}, {
 		.mapbase	= 0xffe10000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 81, 81, 81, 81 },
 		.clk		= "scif1",
 	}, {
 		.mapbase	= 0xffe20000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 82, 82, 82, 82 },
 		.clk		= "scif2",
 	}, {
 		.mapbase	= 0xffe30000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 83, 83, 83, 83 },
 		.clk		= "scif3",

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

@@ -280,6 +280,7 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 80, 80, 80, 80 },
 		.clk		= "scif0",

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

@@ -305,25 +305,25 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 80, 80, 80, 80 },
 		.clk		= "scif0",
-	},
-	{
+	}, {
 		.mapbase	= 0xffe10000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 81, 81, 81, 81 },
 		.clk		= "scif1",
-	},
-	{
+	}, {
 		.mapbase	= 0xffe20000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 82, 82, 82, 82 },
 		.clk		= "scif2",
-	},
-	{
+	}, {
 		.flags = 0,
 	}
 };

arch/sh/kernel/cpu/sh4a/setup-sh7723.c

@@ -321,36 +321,42 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase        = 0xffe00000,
 		.flags          = UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type           = PORT_SCIF,
 		.irqs           = { 80, 80, 80, 80 },
 		.clk		= "scif0",
 	},{
 		.mapbase        = 0xffe10000,
 		.flags          = UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type           = PORT_SCIF,
 		.irqs           = { 81, 81, 81, 81 },
 		.clk		= "scif1",
 	},{
 		.mapbase        = 0xffe20000,
 		.flags          = UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type           = PORT_SCIF,
 		.irqs           = { 82, 82, 82, 82 },
 		.clk		= "scif2",
 	},{
 		.mapbase	= 0xa4e30000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIFA,
 		.irqs		= { 56, 56, 56, 56 },
 		.clk		= "scif3",
 	},{
 		.mapbase	= 0xa4e40000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIFA,
 		.irqs		= { 88, 88, 88, 88 },
 		.clk		= "scif4",
 	},{
 		.mapbase	= 0xa4e50000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIFA,
 		.irqs		= { 109, 109, 109, 109 },
 		.clk		= "scif5",

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

@@ -28,36 +28,42 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase        = 0xffe00000,
 		.flags          = UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type           = PORT_SCIF,
 		.irqs           = { 80, 80, 80, 80 },
 		.clk		= "scif0",
 	}, {
 		.mapbase        = 0xffe10000,
 		.flags          = UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type           = PORT_SCIF,
 		.irqs           = { 81, 81, 81, 81 },
 		.clk		= "scif1",
 	}, {
 		.mapbase        = 0xffe20000,
 		.flags          = UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type           = PORT_SCIF,
 		.irqs           = { 82, 82, 82, 82 },
 		.clk		= "scif2",
 	}, {
 		.mapbase	= 0xa4e30000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIFA,
 		.irqs		= { 56, 56, 56, 56 },
 		.clk		= "scif3",
 	}, {
 		.mapbase	= 0xa4e40000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIFA,
 		.irqs		= { 88, 88, 88, 88 },
 		.clk		= "scif4",
 	}, {
 		.mapbase	= 0xa4e50000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIFA,
 		.irqs		= { 109, 109, 109, 109 },
 		.clk		= "scif5",

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

@@ -40,16 +40,19 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 40, 40, 40 },
 	}, {
 		.mapbase	= 0xffe08000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 76, 76, 76, 76 },
 	}, {
 		.mapbase	= 0xffe10000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 104, 104, 104, 104 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

@@ -18,51 +18,61 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xff923000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 61, 61, 61, 61 },
 	}, {
 		.mapbase	= 0xff924000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 62, 62, 62, 62 },
 	}, {
 		.mapbase	= 0xff925000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 63, 63, 63, 63 },
 	}, {
 		.mapbase	= 0xff926000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 64, 64, 64, 64 },
 	}, {
 		.mapbase	= 0xff927000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 65, 65, 65, 65 },
 	}, {
 		.mapbase	= 0xff928000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 66, 66, 66, 66 },
 	}, {
 		.mapbase	= 0xff929000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 67, 67, 67, 67 },
 	}, {
 		.mapbase	= 0xff92a000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 68, 68, 68, 68 },
 	}, {
 		.mapbase	= 0xff92b000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 69, 69, 69, 69 },
 	}, {
 		.mapbase	= 0xff92c000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 70, 70, 70, 70 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-sh7780.c

@@ -220,11 +220,13 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 40, 40, 40 },
 	}, {
 		.mapbase	= 0xffe10000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 76, 76, 76, 76 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

@@ -202,36 +202,42 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffea0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 40, 40, 40 },
 		.clk		= "scif_fck",
 	}, {
 		.mapbase	= 0xffeb0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 44, 44, 44, 44 },
 		.clk		= "scif_fck",
 	}, {
 		.mapbase	= 0xffec0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 60, 60, 60, 60 },
 		.clk		= "scif_fck",
 	}, {
 		.mapbase	= 0xffed0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 61, 61, 61, 61 },
 		.clk		= "scif_fck",
 	}, {
 		.mapbase	= 0xffee0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 62, 62, 62, 62 },
 		.clk		= "scif_fck",
 	}, {
 		.mapbase	= 0xffef0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 63, 63, 63, 63 },
 		.clk		= "scif_fck",

arch/sh/kernel/cpu/sh4a/setup-sh7786.c

@@ -27,6 +27,7 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffea0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 41, 43, 42 },
 	},
@@ -36,26 +37,31 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffeb0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 44, 44, 44, 44 },
 	}, {
 		.mapbase	= 0xffec0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 50, 50, 50, 50 },
 	}, {
 		.mapbase	= 0xffed0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 51, 51, 51, 51 },
 	}, {
 		.mapbase	= 0xffee0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 52, 52, 52 },
 	}, {
 		.mapbase	= 0xffef0000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 		.type		= PORT_SCIF,
 		.irqs		= { 53, 53, 53, 53 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-shx3.c

@@ -19,21 +19,25 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffc30000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 41, 43, 42 },
 	}, {
 		.mapbase	= 0xffc40000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 44, 45, 47, 46 },
 	}, {
 		.mapbase	= 0xffc50000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 48, 49, 51, 50 },
 	}, {
 		.mapbase	= 0xffc60000,
 		.flags		= UPF_BOOT_AUTOCONF,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 53, 55, 54 },
 	}, {

arch/sh/kernel/cpu/sh5/setup-sh5.c

@@ -20,6 +20,7 @@ static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= PHYS_PERIPHERAL_BLOCK + 0x01030000,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 		.type		= PORT_SCIF,
 		.irqs		= { 39, 40, 42, 0 },
 	}, {

drivers/serial/sh-sci.c

@@ -79,6 +79,9 @@ struct sci_port {
 	struct timer_list	break_timer;
 	int			break_flag;
 
+	/* SCSCR initialization */
+	unsigned int		scscr;
+
 #ifdef CONFIG_HAVE_CLK
 	/* Interface clock */
 	struct clk		*iclk;
@@ -928,6 +931,7 @@ static void sci_shutdown(struct uart_port *port)
 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 			    struct ktermios *old)
 {
+	struct sci_port *s = to_sci_port(port);
 	unsigned int status, baud, smr_val;
 	int t = -1;
 
@@ -972,7 +976,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 	sci_init_pins(port, termios->c_cflag);
 	sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
 
-	sci_out(port, SCSCR, SCSCR_INIT(port));
+	sci_out(port, SCSCR, s->scscr);
 
 	if ((termios->c_cflag & CREAD) != 0)
 		sci_start_rx(port, 0);
@@ -1097,6 +1101,7 @@ static void __devinit sci_init_single(struct platform_device *dev,
 	sci_port->port.mapbase	= p->mapbase;
 	sci_port->port.membase	= p->membase;
 
+	sci_port->scscr		= p->scscr;
 	sci_port->port.irq	= p->irqs[SCIx_TXI_IRQ];
 	sci_port->port.flags	= p->flags;
 	sci_port->port.dev	= &dev->dev;

drivers/serial/sh-sci.h

@@ -15,7 +15,6 @@
     defined(CONFIG_CPU_SUBTYPE_SH7709)
 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
-# define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 # define SCIF0		0xA4400000
 # define SCIF2		0xA4410000
@@ -23,15 +22,8 @@
 # define IRDA_SCIF	SCIF0
 # define SCPCR 0xA4000116
 # define SCPDR 0xA4000136
-
-/* Set the clock source,
- * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
- * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
- */
-# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
       defined(CONFIG_CPU_SUBTYPE_SH7721)
-# define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
 # define PORT_PTCR	   0xA405011EUL
 # define PORT_PVCR	   0xA4050122UL
 # define SCIF_ORER	   0x0200   /* overrun error bit */
@@ -39,7 +31,6 @@
 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
-# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
@@ -49,39 +40,31 @@
 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
-# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
-	0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
-	0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001  /* overrun error bit */
-# define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 # define SCSPTR0 0xA4400000	  /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
 # define PACR 0xa4050100
 # define PBCR 0xa4050102
-# define SCSCR_INIT(port)          0x3B
 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 # define SCSPTR0 0xffe00010	/* 16 bit SCIF */
 # define SCSPTR1 0xffe10010	/* 16 bit SCIF */
 # define SCSPTR2 0xffe20010	/* 16 bit SCIF */
 # define SCSPTR3 0xffe30010	/* 16 bit SCIF */
-# define SCSCR_INIT(port) 0x32	/* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 # define PADR			0xA4050120
 # define PSDR			0xA405013e
 # define PWDR			0xA4050166
 # define PSCR			0xA405011E
 # define SCIF_ORER		0x0001	/* overrun error bit */
-# define SCSCR_INIT(port)	0x0038	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
 # define SCPDR0			0xA405013E      /* 16 bit SCIF0 PSDR */
 # define SCSPTR0		SCPDR0
 # define SCIF_ORER		0x0001  /* overrun error bit */
-# define SCSCR_INIT(port)	0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 # define SCSPTR0                0xa4050160
 # define SCSPTR1                0xa405013e
@@ -90,45 +73,34 @@
 # define SCSPTR4                0xa4050128
 # define SCSPTR5                0xa4050128
 # define SCIF_ORER              0x0001  /* overrun error bit */
-# define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
 # define SCIF_ORER              0x0001  /* overrun error bit */
-# define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
-# define SCIF_BASE_ADDR    0x01030000
-# define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 # define SCIF_PTR2_OFFS    0x0000020
 # define SCIF_LSR2_OFFS    0x0000024
 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
-# define SCSCR_INIT(port)  0x38		/* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
-# define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 #elif defined(CONFIG_H8S2678)
-# define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
 # define SCIF_ORER 0x0001  /* overrun error bit */
-# define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001  /* overrun error bit */
-# define SCSCR_INIT(port)	0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 # define SCSPTR0	0xffe00024	/* 16 bit SCIF */
 # define SCSPTR1	0xffe10024	/* 16 bit SCIF */
 # define SCIF_ORER	0x0001		/* Overrun error bit */
-# define SCSCR_INIT(port)	0x3a	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
       defined(CONFIG_CPU_SUBTYPE_SH7786)
 # define SCSPTR0	0xffea0024	/* 16 bit SCIF */
@@ -138,7 +110,6 @@
 # define SCSPTR4	0xffee0024	/* 16 bit SCIF */
 # define SCSPTR5	0xffef0024	/* 16 bit SCIF */
 # define SCIF_ORER	0x0001		/* Overrun error bit */
-# define SCSCR_INIT(port)	0x3a	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
       defined(CONFIG_CPU_SUBTYPE_SH7203) || \
       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
@@ -153,20 +124,17 @@
 #  define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
 #  define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
 # endif
-# define SCSCR_INIT(port)	0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001  /* overrun error bit */
-# define SCSCR_INIT(port)	0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 # define SCSPTR0 0xffc30020		/* 16 bit SCIF */
 # define SCSPTR1 0xffc40020		/* 16 bit SCIF */
 # define SCSPTR2 0xffc50020		/* 16 bit SCIF */
 # define SCSPTR3 0xffc60020		/* 16 bit SCIF */
 # define SCIF_ORER 0x0001		/* Overrun error bit */
-# define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #else
 # error CPU subtype not defined
 #endif

include/linux/serial_sci.h

@@ -7,6 +7,15 @@
  * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
  */
 
+#define SCSCR_TIE	(1 << 7)
+#define SCSCR_RIE	(1 << 6)
+#define SCSCR_TE	(1 << 5)
+#define SCSCR_RE	(1 << 4)
+#define SCSCR_REIE	(1 << 3)
+#define SCSCR_TOIE	(1 << 2)	/* not supported by all parts */
+#define SCSCR_CKE1	(1 << 1)
+#define SCSCR_CKE0	(1 << 0)
+
 /* Offsets into the sci_port->irqs array */
 enum {
 	SCIx_ERI_IRQ,
@@ -26,6 +35,8 @@ struct plat_sci_port {
 	unsigned int	type;			/* SCI / SCIF / IRDA */
 	upf_t		flags;			/* UPF_* flags */
 	char		*clk;			/* clock string */
+
+	unsigned int	scscr;			/* SCSCR initialization */
 };
 
 #endif /* __LINUX_SERIAL_SCI_H */