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006a851b
cloud-kernel
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体验新版 GitCode,发现更多精彩内容 >>
提交
006a851b
编写于
6月 26, 2012
作者:
S
Steven J. Hill
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
MIPS: Add support for the 1074K core.
Signed-off-by:
N
Steven J. Hill
<
sjhill@mips.com
>
上级
fea7a08a
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
28 addition
and
0 deletion
+28
-0
arch/mips/include/asm/cpu.h
arch/mips/include/asm/cpu.h
+1
-0
arch/mips/include/asm/mipsregs.h
arch/mips/include/asm/mipsregs.h
+2
-0
arch/mips/kernel/cpu-probe.c
arch/mips/kernel/cpu-probe.c
+4
-0
arch/mips/mm/c-r4k.c
arch/mips/mm/c-r4k.c
+21
-0
未找到文件。
arch/mips/include/asm/cpu.h
浏览文件 @
006a851b
...
...
@@ -94,6 +94,7 @@
#define PRID_IMP_24KE 0x9600
#define PRID_IMP_74K 0x9700
#define PRID_IMP_1004K 0x9900
#define PRID_IMP_1074K 0x9a00
#define PRID_IMP_M14KC 0x9c00
/*
...
...
arch/mips/include/asm/mipsregs.h
浏览文件 @
006a851b
...
...
@@ -596,6 +596,8 @@
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
...
...
arch/mips/kernel/cpu-probe.c
浏览文件 @
006a851b
...
...
@@ -857,6 +857,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
c
->
cputype
=
CPU_1004K
;
__cpu_name
[
cpu
]
=
"MIPS 1004Kc"
;
break
;
case
PRID_IMP_1074K
:
c
->
cputype
=
CPU_74K
;
__cpu_name
[
cpu
]
=
"MIPS 1074Kc"
;
break
;
}
spram_config
();
...
...
arch/mips/mm/c-r4k.c
浏览文件 @
006a851b
...
...
@@ -786,6 +786,25 @@ static inline void rm7k_erratum31(void)
}
}
static
inline
void
alias_74k_erratum
(
struct
cpuinfo_mips
*
c
)
{
/*
* Early versions of the 74K do not update the cache tags on a
* vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
* aliases. In this case it is better to treat the cache as always
* having aliases.
*/
if
((
c
->
processor_id
&
0xff
)
<=
PRID_REV_ENCODE_332
(
2
,
4
,
0
))
c
->
dcache
.
flags
|=
MIPS_CACHE_VTAG
;
if
((
c
->
processor_id
&
0xff
)
==
PRID_REV_ENCODE_332
(
2
,
4
,
0
))
write_c0_config6
(
read_c0_config6
()
|
MIPS_CONF6_SYND
);
if
(((
c
->
processor_id
&
0xff00
)
==
PRID_IMP_1074K
)
&&
((
c
->
processor_id
&
0xff
)
<=
PRID_REV_ENCODE_332
(
1
,
1
,
0
)))
{
c
->
dcache
.
flags
|=
MIPS_CACHE_VTAG
;
write_c0_config6
(
read_c0_config6
()
|
MIPS_CONF6_SYND
);
}
}
static
char
*
way_string
[]
__cpuinitdata
=
{
NULL
,
"direct mapped"
,
"2-way"
,
"3-way"
,
"4-way"
,
"5-way"
,
"6-way"
,
"7-way"
,
"8-way"
};
...
...
@@ -1056,6 +1075,8 @@ static void __cpuinit probe_pcache(void)
case
CPU_34K
:
case
CPU_74K
:
case
CPU_1004K
:
if
(
c
->
cputype
==
CPU_74K
)
alias_74k_erratum
(
c
);
if
((
read_c0_config7
()
&
(
1
<<
16
)))
{
/* effectively physically indexed dcache,
thus no virtual aliases. */
...
...
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