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    drm/i915: Added write-enable pte bit supportt · 24f3a8cf
    Akash Goel 提交于
    This adds support for a write-enable bit in the entry of GTT.
    This is handled via a read-only flag in the GEM buffer object which
    is then used to see how to set the bit when writing the GTT entries.
    Currently by default the Batch buffer & Ring buffers are marked as read only.
    
    v2: Moved the pte override code for read-only bit to 'byt_pte_encode'. (Chris)
        Fixed the issue of leaving 'gt_old_ro' as unused. (Chris)
    
    v3: Removed the 'gt_old_ro' field, now setting RO bit only for Ring Buffers(Daniel).
    
    v4: Added a new 'flags' parameter to all the pte(gen6) encode & insert_entries functions,
        in lieu of overloading the cache_level enum (Daniel).
    
    v5: Removed the superfluous VLV check & changed the definition location of PTE_READ_ONLY flag (Imre)
    Reviewed-by: NImre Deak <imre.deak@intel.com>
    Signed-off-by: NAkash Goel <akash.goel@intel.com>
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    24f3a8cf
intel_ringbuffer.c 64.7 KB