Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP.  This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.
Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: Added defconfig]
Signed-off-by: NStafford Horne <shorne@gmail.com>