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    KVM: PPC: Book3S HV: Refine barriers in guest entry/exit · f019b7ad
    Paul Mackerras 提交于
    Some users have reported instances of the host hanging with secondary
    threads of a core waiting for the primary thread to exit the guest,
    and the primary thread stuck in nap mode.  This prompted a review of
    the memory barriers in the guest entry/exit code, and this is the
    result.  Most of these changes are the suggestions of Dean Burdick
    <deanburdick@us.ibm.com>.
    
    The barriers between updating napping_threads and reading the
    entry_exit_count on the one hand, and updating entry_exit_count and
    reading napping_threads on the other, need to be isync not lwsync,
    since we need to ensure that either the napping_threads update or the
    entry_exit_count update get seen.  It is not sufficient to order the
    load vs. lwarx, as lwsync does; we need to order the load vs. the
    stwcx., so we need isync.
    
    In addition, we need a full sync before sending IPIs to wake other
    threads from nap, to ensure that the write to the entry_exit_count is
    visible before the IPI occurs.
    Signed-off-by: NPaul Mackerras <paulus@samba.org>
    Signed-off-by: NAlexander Graf <agraf@suse.de>
    f019b7ad
book3s_hv_rmhandlers.S 45.9 KB