If the buffer needing cache invalidation for inbound DMA does start or
end on a cache line aligned address, we need to use the non-destructive
clean&invalidate operation. This issue was introduced by commit
7363590d (arm64: Implement coherent DMA API based on swiotlb).
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Reported-by: NJon Medhurst (Tixy) <tixy@linaro.org>