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    x86/cqm: Share PQR_ASSOC related data between CQM and CAT · 6b281569
    Fenghua Yu 提交于
    PQR_ASSOC MSR contains the RMID used for preformance monitoring of cache
    occupancy and memory bandwidth. The upper 32bit of this MSR contain the
    CLOSID for cache allocation. So we need to share the information between
    the two facilities.
    
    Move the rdt data structure declaration into the shared header file and
    make the per cpu data structure containing the MSR values global.
    Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
    Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com>
    Cc: "Tony Luck" <tony.luck@intel.com>
    Cc: "David Carrillo-Cisneros" <davidcc@google.com>
    Cc: "Sai Prakhya" <sai.praneeth.prakhya@intel.com>
    Cc: "Peter Zijlstra" <peterz@infradead.org>
    Cc: "Stephane Eranian" <eranian@google.com>
    Cc: "Dave Hansen" <dave.hansen@intel.com>
    Cc: "Shaohua Li" <shli@fb.com>
    Cc: "Nilay Vaish" <nilayvaish@gmail.com>
    Cc: "Vikas Shivappa" <vikas.shivappa@linux.intel.com>
    Cc: "Ingo Molnar" <mingo@elte.hu>
    Cc: "Borislav Petkov" <bp@suse.de>
    Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>
    Link: http://lkml.kernel.org/r/1477142405-32078-10-git-send-email-fenghua.yu@intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
    6b281569
cqm.c 43.0 KB