On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as:

Lcd Pixel clock = DISPC_FCLK / lcd / pcd

Where lcd and pcd are divisors in the DISPC_DIVISOR register.

On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new
clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as:

Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2

Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers.

LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL
and DSI2 PLL as clock sources respectively. Introduce functions to select and
get the clock source for these new clocks. Modify DISPC functions get the
correct lck and pck rates based on the clock source of these clocks. Since
OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source
as DSS_CLK_SRC_FCK by introducing a dss feature.

Introduce clock source names for OMAP4 and some register field changes in
DSS_CTRL on OMAP4.

Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL
functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as
clock.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>