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    mmc: sd: Meet alignment requirements for raw_ssr DMA · e85baa88
    Paul Burton 提交于
    The mmc_read_ssr() function results in DMA to the raw_ssr member of
    struct mmc_card, which is not guaranteed to be cache line aligned & thus
    might not meet the requirements set out in Documentation/DMA-API.txt:
    
      Warnings:  Memory coherency operates at a granularity called the cache
      line width.  In order for memory mapped by this API to operate
      correctly, the mapped region must begin exactly on a cache line
      boundary and end exactly on one (to prevent two separately mapped
      regions from sharing a single cache line).  Since the cache line size
      may not be known at compile time, the API will not enforce this
      requirement.  Therefore, it is recommended that driver writers who
      don't take special care to determine the cache line size at run time
      only map virtual regions that begin and end on page boundaries (which
      are guaranteed also to be cache line boundaries).
    
    On some systems where DMA is non-coherent this can lead to us losing
    data that shares cache lines with the raw_ssr array.
    
    Fix this by kmalloc'ing a temporary buffer to perform DMA into. kmalloc
    will ensure the buffer is suitably aligned, allowing the DMA to be
    performed without any loss of data.
    Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
    Fixes: 5275a652 ("mmc: sd: Export SD Status via “ssr” device attribute")
    Cc: <stable@vger.kernel.org>
    Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
    e85baa88
sd.c 29.1 KB