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由 Andy Walls 提交于
The SYS and AUX PLLs need to be initialized to different values based on the chip: CX23885, CX23887, CX23888, as each uses a different crystal frequency: 28.6363 MHz, 25.0 MHz, 50.0 MHz. Signed-off-by: NAndy Walls <awalls@radix.net> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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