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    MIPS: Add defs & probing of BadInstr[P] registers · e06a1548
    James Hogan 提交于
    The optional CP0_BadInstr and CP0_BadInstrP registers are written with
    the encoding of the instruction that caused a synchronous exception to
    occur, and the prior branch instruction if in a delay slot.
    
    These will be useful for instruction emulation in KVM, and especially
    for VZ support where reading guest virtual memory is a bit more awkward.
    
    Add CPU option numbers and cpu_has_* definitions to indicate the
    presence of each registers, and add code to probe for them using bits in
    the CP0_Config3 register.
    
    [ralf@linux-mips.org: resolve merge conflict.]
    Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/13224/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    e06a1548
mipsregs.h 63.3 KB