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    sparc64: Validate linear D-TLB misses. · d8ed1d43
    David S. Miller 提交于
    When page alloc debugging is not enabled, we essentially accept any
    virtual address for linear kernel TLB misses.  But with kgdb, kernel
    address probing, and other facilities we can try to access arbitrary
    crap.
    
    So, make sure the address we miss on will translate to physical memory
    that actually exists.
    
    In order to make this work we have to embed the valid address bitmap
    into the kernel image.  And in order to make that less expensive we
    make an adjustment, in that the max physical memory address is
    decreased to "1 << 41", even on the chips that support a 42-bit
    physical address space.  We can do this because bit 41 indicates
    "I/O space" and thus covers non-memory ranges.
    
    The result of this is that:
    
    1) kpte_linear_bitmap shrinks from 2K to 1K in size
    
    2) we need 64K more for the valid address bitmap
    
    We can't let the valid address bitmap be dynamically allocated
    once we start using it to validate TLB misses, otherwise we have
    crazy issues to deal with wrt. recursive TLB misses and such.
    
    If we're in a TLB miss it could be the deepest trap level that's legal
    inside of the cpu.  So if we TLB miss referencing the bitmap, the cpu
    will be out of trap levels and enter RED state.
    
    To guard against out-of-range accesses to the bitmap, we have to check
    to make sure no bits in the physical address above bit 40 are set.  We
    could export and use last_valid_pfn for this check, but that's just an
    unnecessary extra memory reference.
    
    On the plus side of all this, since we load all of these translations
    into the special 4MB mapping TSB, and we check the TSB first for TLB
    misses, there should be absolutely no real cost for these new checks
    in the TLB miss path.
    
    Reported-by: heyongli@gmail.com
    Signed-off-by: NDavid S. Miller <davem@davemloft.net>
    d8ed1d43
pgtable_64.h 23.7 KB