* This patch fixes a bug in calculating the scaled
  power for three chain chipsets.

* Also, a delay is needed after setting DAC low-power mode in
  TOP1 RF register (Top Level Register Bits).
Signed-off-by: NSenthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>