An aligned data buffer is such where the Ethernet portion of the packet
starts on a 4-byte boundary. Some chip families support padding the Rx
data buffer to achieve such alignment, others rely on the host to perform
it.
Implement the HW op for getting alignment state in wl12xx. Add
support for HW-padded alignment in the Rx flow.
Signed-off-by: NArik Nemtsov <arik@wizery.com>
Signed-off-by: NLuciano Coelho <coelho@ti.com>