This patch fixes the DP AUX CH timeouts observed during CI IGT
tests thus fixing the CI failures. This is done by adding a
quirk for a particular PCI device that requires the panel power
cycle delay (T12) to be set to 800ms which is 300msecs more than
the minimum value specified in the eDP spec. So a quirk is
implemented for that specific PCI device.

v4:
* Add Bugzilla links for FDO bugs in the commit message (Ville, Jani)
v3:
* Change some comments, specify the delay as 800 * 10 (Ville)
v2:
* Change the function and variable names to from PPS_T12_
to _T12 since it is a T12 delay (Clint)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101144
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101154
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101167
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101515
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: NManasi Navare <manasi.d.navare@intel.com>
Reviewed-by: NClinton Taylor <clinton.a.taylor@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1498840428-23176-1-git-send-email-manasi.d.navare@intel.comSigned-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>