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    PCI: Turn off Request Attributes to avoid Chelsio T5 Completion erratum · c56d4450
    Hariprasad Shenai 提交于
    The Chelsio T5 has a PCIe compliance erratum that causes Malformed TLP or
    Unexpected Completion errors in some systems, which may cause device access
    timeouts.
    
    Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same values
    for the Attribute as were supplied in the header of the corresponding
    Request, except as explicitly allowed when IDO is used."
    
    Instead of copying the Attributes from the Request to the Completion, the
    T5 always generates Completions with zero Attributes.  The receiver of a
    Completion whose Attributes don't match the Request may accept it (which
    itself seems non-compliant based on sec 2.3.2), or it may handle it as a
    Malformed TLP or an Unexpected Completion, which will probably lead to a
    device access timeout.
    
    Work around this by disabling "Relaxed Ordering" and "No Snoop" in the Root
    Port so it always generate Requests with zero Attributes.
    
    This does affect all other devices which are downstream of that Root Port,
    but these are performance optimizations that should not make a functional
    difference.
    
    Note that Configuration Space accesses are never supposed to have TLP
    Attributes, so we're safe waiting till after any Configuration Space
    accesses to do the Root Port "fixup".
    
    Based on original work by Casey Leedom <leedom@chelsio.com>
    
    [bhelgaas: changelog, comments, rename to pci_find_pcie_root_port(), rework
    to use pci_upstream_bridge() and check for Root Port device type, edit
    diagnostics to clarify intent and devices affected]
    Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com>
    Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
    c56d4450
pci.c 119.8 KB