• S
    powerpc/e6500: hw tablewalk: clear TID in kernel indirect entries · bbd08c72
    Scott Wood 提交于
    Previously TID was being cleared before the tlbsx, but not after.  This
    can lead to a multiway hit between a TLB entry with TID=0 (previously
    inserted when PID=0) and a TLB entry with TID!=0 that matches PID.
    This can theoretically result in undefined behavior, though we probably
    get lucky due to the details of the overlap.  It also results in the
    inability to use multihit detection to detect other conflicting TLB
    entries, as well as poorer TLB utilization due to duplicating kernel
    TLB entries.
    
    Rather than try to patch up MAS1 after tlbsx, the entire value is
    saved/restored as with MAS2.
    
    I observed a slight improvement in TLB miss performance with this patch
    applied.
    Signed-off-by: NScott Wood <scottwood@freescale.com>
    Reported-by: NEd Swarthout <ed.swarthout@freescale.com>
    bbd08c72
tlb_low_64e.S 34.2 KB