This code makes use of the SDM fractional divider if present to
constrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.

Based on original work by Aleksandr Frid <afrid@nvidia.com>
Signed-off-by: NBill Huang <bilhuang@nvidia.com>
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>