When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the
register shall be left un-touched, but it does not mean the clock
should stop rate propagation if CLK_SET_RATE_PARENT is set

This is properly handled in qcom clk-regmap-divider but it was not in
the generic divider

To fix this situation, introduce a new helper function
divider_ro_round_rate, on the same model as divider_round_rate.

Fixes: e6d5e7d9 ("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Tested-By: NDavid Lechner <david@lechnology.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>