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    drm/i915/icl: new context descriptor support · ac52da6a
    Daniele Ceraolo Spurio 提交于
    Starting from Gen11 the context descriptor format has been updated in
    the HW. The hw_id field has been considerably reduced in size and engine
    class and instance fields have been added.
    
    There is a slight name clashing issue because the field that we call
    hw_id is actually called SW Context ID in the specs for Gen11+.
    
    With the current size of the hw_id field we can have a maximum of 2k
    contexts at any time, but we could use the sw_counter field (which is sw
    defined) to increase that because the HW requirement is that
    engine_id + sw id + sw_counter is a unique number.
    GuC uses a similar method to support more contexts but does its tracking
    at lrc level. To avoid doing an implementation that will need to be
    reworked once GuC support lands, defer it for now and mark it as TODO.
    
    v2: rebased, add documentation, fix GEN11_ENGINE_INSTANCE_SHIFT
    v3: rebased, bring back lost code from i915_gem_context.c
    v4: make TODO comment more generic
    v5: be consistent with bit ordering, add extra checks (Chris)
    
    Cc: Oscar Mateo <oscar.mateo@intel.com>
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
    Signed-off-by: NDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
    Reviewed-by: NOscar Mateo <oscar.mateo@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20180302161501.28594-3-mika.kuoppala@linux.intel.comSigned-off-by: NMika Kuoppala <mika.kuoppala@linux.intel.com>
    ac52da6a
intel_engine_cs.c 58.0 KB