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    PCI: mvebu: Disable prefetchable memory support in PCI-to-PCI bridge · 36dd1f3e
    Thomas Petazzoni 提交于
    The Marvell PCIe driver uses an emulated PCI-to-PCI bridge to be able
    to dynamically set up MBus address decoding windows for PCI I/O and
    memory regions depending on the PCI devices enumerated by Linux.
    
    However, this emulated PCI-to-PCI bridge logic makes the Linux PCI
    core believe that prefetchable memory regions are supported (because
    the registers are read/write), while in fact no adress decoding window
    is ever created for such regions. Since the Marvell MBus address
    decoding windows do not distinguish memory regions and prefetchable
    memory regions, this patch takes a simple approach: change the
    PCI-to-PCI bridge emulation to let the Linux PCI core know that we
    don't support prefetchable memory regions.
    
    To achieve this, we simply make the prefetchable memory base a
    read-only register that always returns 0. Reading/writing all the
    other prefetchable memory related registers has no effect.
    
    This problem was originally reported by Finn Hoffmann
    <finn@uni-bremen.de>, who couldn't get a RTL8111/8168B PCI NIC working
    on the NSA310 Kirkwood platform after updating to 3.11-rc. The problem
    was that the PCI-to-PCI bridge emulation was making the Linux PCI core
    believe that we support prefetchable memory, so the Linux PCI core was
    only filling the prefetchable memory base and limit registers, which
    does not lead to a MBus window being created. The below patch has been
    confirmed by Finn Hoffmann to fix his problem on Kirkwood, and has
    otherwise been successfully tested on the Armada XP GP platform with a
    e1000e PCIe NIC and a Marvell SATA PCIe card.
    Reported-by: NFinn Hoffmann <finn@uni-bremen.de>
    Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
    36dd1f3e
pci-mvebu.c 22.5 KB