• R
    apic, x86: Check if EILVT APIC registers are available (AMD only) · a68c439b
    Robert Richter 提交于
    This patch implements checks for the availability of LVT entries
    (APIC500-530) and reserves it if used. The check becomes
    necessary since we want to let the BIOS provide the LVT offsets.
     The offsets should be determined by the subsystems using it
    like those for MCE threshold or IBS.  On K8 only offset 0
    (APIC500) and MCE interrupts are supported. Beginning with
    family 10h at least 4 offsets are available.
    
    Since offsets must be consistent for all cores, we keep track of
    the LVT offsets in software and reserve the offset for the same
    vector also to be used on other cores. An offset is freed by
    setting the entry to APIC_EILVT_MASKED.
    
    If the BIOS is right, there should be no conflicts. Otherwise a
    "[Firmware Bug]: ..." error message is generated. However, if
    software does not properly determines the offsets, it is not
    necessarily a BIOS bug.
    Signed-off-by: NRobert Richter <robert.richter@amd.com>
    LKML-Reference: <1286360874-1471-2-git-send-email-robert.richter@amd.com>
    Signed-off-by: NIngo Molnar <mingo@elte.hu>
    a68c439b
apic.c 56.5 KB