• J
    MIPS: Lantiq: add SoC specific code for XWAY family · 8ec6d935
    John Crispin 提交于
    Add support for the Lantiq XWAY family of Mips24KEc SoCs.
    
    * Danube (PSB50702)
    * Twinpass (PSB4000)
    * AR9 (PSB50802)
    * Amazon SE (PSB5061)
    
    The Amazon SE is a lightweight SoC and has no PCI as well as a different
    clock. We split the code out into seperate files to handle this.
    
    The GPIO pins on the SoCs are multi function and there are several bits
    we can use to configure the pins. To be as compatible as possible to
    GPIOLIB we add a function
    
    int lq_gpio_request(unsigned int pin, unsigned int alt0,
            unsigned int alt1, unsigned int dir, const char *name);
    
    which lets you configure the 2 "alternate function" bits. This way drivers like
    PCI can make use of GPIOLIB without a cubersome wrapper.
    
    The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was
    taken from a 2.4.20 source tree and was never really changed by me since then.
    Signed-off-by: NJohn Crispin <blogic@openwrt.org>
    Signed-off-by: NRalph Hempel <ralph.hempel@lantiq.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/2249/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    8ec6d935
irq.h 381 字节