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由 Kevin Hilman 提交于
Ensure the clock rate that will be used is a valid one before attempting to scale the voltage. Currently the driver assumes it has a valid frequency from the OPP table, but boards using different system oscillators might not have exact matches with the OPP table, and result in a failing call to clk_set_rate(). This is particularily bad because the voltage may be scaled even though the frequency is not. This will obviously lead to some unpredictable behavior, especially if the frequency is high and the voltage is dropped. Thanks to Joni Lapilainen for reporting crashes seen on 3430/n900. Reported-by: NJoni Lapilainen <joni.lapilainen@gmail.com> Acked-by: NRafael J. Wysocki <rjw@sisk.pl> Signed-off-by: NKevin Hilman <khilman@ti.com>
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