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    arm64: traps: correctly handle MRS/MSR with XZR · 8b6e70fc
    Mark Rutland 提交于
    Currently we hand-roll XZR-safe register handling in
    user_cache_maint_handler(), though we forget to do the same in
    ctr_read_handler(), and may erroneously write back to the user SP rather
    than XZR.
    
    Use the new helpers to handle these cases correctly and consistently.
    Signed-off-by: NMark Rutland <mark.rutland@arm.com>
    Fixes: 116c81f4 ("arm64: Work around systems with mismatched cache line sizes")
    Cc: Andre Przywara <andre.przywara@arm.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Marc Zyngier <marc.zyngier@arm.com>
    Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
    Cc: Will Deacon <will.deacon@arm.com>
    Signed-off-by: NWill Deacon <will.deacon@arm.com>
    8b6e70fc
traps.c 17.2 KB