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由 Daniel Schultz 提交于
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. Signed-off-by: NDaniel Schultz <d.schultz@phytec.de> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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