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    ARM: 6185/1: AT91: PM: dual ram controller support · 7dca3343
    Nicolas Ferre 提交于
    This rework allows to address tow memory controllers. AT91SAM9263 and
    AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management
    should take care of this.
    This patch modify the way RAM IP header files are implemented to allow
    access to registers of both controllers ; it also adds some macros.
    
    We also modify the power management files to use those modified header files.
    Slow clock (assembly) and regular power management functions are synchronized
    for setting of RAM self-refresh procedure:
    (lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESH
    
    Note that AT91RM9200 is not impacted by this modification.
    Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
    Acked-by: NAndrew Victor <linux@maxim.org.za>
    Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
    7dca3343
at91sam9260.h 5.5 KB