This board is based on Juno r0 with updated Cortex A5x revisions
and board errata fixes. It also contains coherent ThinLinks ports
on the expansion slot that allow for an AXI master on the daughter
card to participate in a coherency domain.

Support for SoC PCIe host bridge will be added as a separate series.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Acked-by: NJon Medhurst <tixy@linaro.org>
Acked-by: NSudeep Holla <sudeep.holla@arm.com>