• S
    [POWERPC] 8xx: Work around CPU15 erratum. · 74016852
    Scott Wood 提交于
    The CPU15 erratum on MPC8xx chips can cause incorrect code execution
    under certain circumstances, where there is a conditional or indirect
    branch in the last word of a page, with a target in the last cache line
    of the next page.  This patch implements one of the suggested
    workarounds, by forcing a TLB miss whenever execution crosses a page
    boundary.  This is done by invalidating the pages before and after the
    one being loaded into the TLB in the ITLB miss handler.
    Signed-off-by: NScott Wood <scottwood@freescale.com>
    Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
    74016852
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