This patch makes the initial changes required to workaround TSC-false
pen-up interrupts. It is required to implement these changes in order to
remove udelay in the TSC interrupt handler and false pen-up events.  The
charge step is to be executed immediately after sampling X+. Hence TSC is
made to use higher numbered steps (steps 5 to 16 for 5 co-ordinate
readouts, 4 wire TSC configuration) and ADC to use lower ones. Further X
co-ordinate readouts must be the last to be sampled, thus co-ordinates are
sampled in the order Y-Z-X.
Signed-off-by: NBrad Griffis <bgriffis@ti.com>
[vigneshr@ti.com: Ported the patch from v3.12 to v3.19rc1]
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: NJonathan Cameron <jic23@kernel.org>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>