• B
    powerpc/mm: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED · 64b3d0e8
    Benjamin Herrenschmidt 提交于
    Currently, we never set _PAGE_COHERENT in the PTEs, we just OR it in
    in the hash code based on some CPU feature bit.  We also manipulate
    _PAGE_NO_CACHE and _PAGE_GUARDED by hand in all sorts of places.
    
    This changes the logic so that instead, the PTE now contains
    _PAGE_COHERENT for all normal RAM pages thay have I = 0 on platforms
    that need it.  The hash code clears it if the feature bit is not set.
    
    It also adds some clean accessors to setup various valid combinations
    of access flags and change various bits of code to use them instead.
    
    This should help having the PTE actually containing the bit
    combinations that we really want.
    
    I also removed _PAGE_GUARDED from _PAGE_BASE on 44x and instead
    set it explicitely from the TLB miss.  I will ultimately remove it
    completely as it appears that it might not be needed after all
    but in the meantime, having it in the TLB miss makes things a
    lot easier.
    Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
    Acked-by: NKumar Gala <galak@kernel.crashing.org>
    Signed-off-by: NPaul Mackerras <paulus@samba.org>
    64b3d0e8
pci-common.c 42.6 KB