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    Documentation: arm: define DT idle states bindings · 3f8161b2
    Lorenzo Pieralisi 提交于
    ARM based platforms implement a variety of power management schemes that
    allow processors to enter idle states at run-time.
    The parameters defining these idle states vary on a per-platform basis forcing
    the OS to hardcode the state parameters in platform specific static tables
    whose size grows as the number of platforms supported in the kernel increases
    and hampers device drivers standardization.
    
    Therefore, this patch aims at standardizing idle state device tree bindings
    for ARM platforms. Bindings define idle state parameters inclusive of entry
    methods and state latencies, to allow operating systems to retrieve the
    configuration entries from the device tree and initialize the related power
    management drivers, paving the way for common code in the kernel to deal with
    idle states and removing the need for static data in current and previous
    kernel versions.
    
    ARM64 platforms require the DT to define an entry-method property
    for idle states.
    
    On system implementing PSCI as an enable-method to enter low-power
    states the PSCI CPU suspend method requires the power_state parameter to
    be passed to the PSCI CPU suspend function.
    
    This parameter is specific to a power state and platform specific,
    therefore must be provided by firmware to the OS in order to enable
    proper call sequence.
    
    Thus, this patch also adds a property in the PSCI bindings that
    describes how the PSCI CPU suspend power_state parameter should be
    defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
    Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
    Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
    Acked-by: NNicolas Pitre <nico@linaro.org>
    Reviewed-by: NRob Herring <robh@kernel.org>
    Reviewed-by: NSebastian Capella <sebcape@gmail.com>
    Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
    3f8161b2
cpus.txt 9.9 KB