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    PCI: iommu: iotlb flushing · 5e0d2a6f
    mark gross 提交于
    This patch is for batching up the flushing of the IOTLB for the DMAR
    implementation found in the Intel VT-d hardware.  It works by building a list
    of to be flushed IOTLB entries and a bitmap list of which DMAR engine they are
    from.
    
    After either a high water mark (250 accessible via debugfs) or 10ms the list
    of iova's will be reclaimed and the DMAR engines associated are IOTLB-flushed.
    
    This approach recovers 15 to 20% of the performance lost when using the IOMMU
    for my netperf udp stream benchmark with small packets.  It can be disabled
    with a kernel boot parameter "intel_iommu=strict".
    
    Its use does weaken the IOMMU protections a bit.
    Signed-off-by: NMark Gross <mgross@linux.intel.com>
    Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
    Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
    5e0d2a6f
intel-iommu.c 57.8 KB