Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.
Signed-off-by: NRick Altherr <raltherr@google.com>
Tested-by: NXo Wang <xow@google.com>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>