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    OMAP: hwmod: Add hardreset management support · 5365efbe
    Benoît Cousson 提交于
    Most processor IPs does have a hardreset signal controlled by the PRM.
    This is different of the softreset used for local IP reset from the
    SYSCONFIG register.
    The granularity can be much finer than orginal HWMOD, for ex, the IVA
    hwmod contains 3 reset lines, the IPU 3 as well, the DSP 2...
    Since this granularity is needed by the driver, we have to ensure
    than one hwmod exist for each hardreset line.
    
    - Store reset lines as hwmod resources that a driver can query by name like
      an irq or sdma line.
    
    - Add two functions for asserting / deasserting reset lines in hwmods
      processor that require manual reset control.
    - Add one functions to get the current reset state.
    - If an hwmod contains only one line, an automatic assertion / de-assertion
      is done.
      -> de-assert the hardreset line only during enable from disable transition
      -> assert the hardreset line only during shutdown
    
    Note: The hwmods with hardreset line and HWMOD_INIT_NO_RESET flag must be
    kept in INITIALIZED state.
    They can be properly enabled only if the hardreset line is de-asserted
    before.
    
    For information here is the list of IPs with HW reset control
    on an OMAP4430 device:
    
    RM_DSP_RSTCTRL
      1,1,'RST2','RW','1','DSP - MMU, cache and slave interface reset control'
      0,0,'RST1','RW','1','DSP - DSP reset control'
    
    RM_IVA_RSTCTRL
      2,2,'RST3','RW','1','IVA logic and SL2 reset control'
      1,1,'RST2','RW','1','IVA Sequencer2 reset control'
      0,0,'RST1','RW','1','IVA sequencer1 reset control'
    
    RM_IPU_RSTCTRL
      2,2,'RST3','RW','1','IPU MMU and CACHE interface reset control.'
      1,1,'RST2','RW','1','IPU Cortex M3 CPU2  reset control.'
      0,0,'RST1','RW','1','IPU Cortex M3 CPU1  reset control.'
    
    PRM_RSTCTRL
      1,1,'RST_GLOBAL_COLD_SW','RW','0','Global COLD software reset control.'
      0,0,'RST_GLOBAL_WARM_SW','RW','0','Global WARM software reset control.'
    
    RM_CPU0_CPU0_RSTCTRL
    RM_CPU1_CPU1_RSTCTRL
      0,0,'RST','RW','0','Cortex A9 CPU0&1 warm local reset control'
    Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
    [paul@pwsan.com: made the hardreset functions static; moved the register
     twiddling into prm*.c functions in previous patches; changed the
     function names to conform with hwmod practice]
    Signed-off-by: NPaul Walmsley <paul@pwsan.com>
    Cc: Kevin Hilman <khilman@deeprootsystems.com>
    Cc: Rajendra Nayak <rnayak@ti.com>
    5365efbe
omap_hwmod.h 19.0 KB