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    mlxsw: pci: Correctly determine if descriptor queue is full · 5091730d
    Ido Schimmel 提交于
    The descriptor queues for sending (SDQs) and receiving (RDQs) packets
    are managed by two counters - producer and consumer - which are both
    16-bit in size. A queue is considered full when the difference between
    the two equals the queue's maximum number of descriptors.
    
    However, if the producer counter overflows, then it's possible for the
    full queue check to fail, as it doesn't take the overflow into account.
    In such a case, descriptors already passed to the device - but for which
    a completion has yet to be posted - will be overwritten, thereby causing
    undefined behavior. The above can be achieved under heavy load (~30
    netperf instances).
    
    Fix that by casting the subtraction result to u16, preventing it from
    being treated as a signed integer.
    
    Fixes: eda6500a ("mlxsw: Add PCI bus implementation")
    Signed-off-by: NIdo Schimmel <idosch@mellanox.com>
    Signed-off-by: NJiri Pirko <jiri@mellanox.com>
    Signed-off-by: NDavid S. Miller <davem@davemloft.net>
    5091730d
pci.c 50.0 KB